2024 J MICRO

Lithography hotspot detection through multi-scale feature fusion utilizing feature pyramid network and dense block

Author: Hui Xu, Ye Yuan, Ruijun Ma, Pan Qi, Fuxin Tang, Xinzhong Xiao, Wenxin Huang, Huaguo Liang

Affiliation: Anhui University of Science and Technology, School of Computer Science and Engineering, Huainan, China; Hefei University of Technology, School of Microelectronics, Hefei, China

Abstract:

Lithography hotspot (LHS) detection is crucial for achieving manufacturability design in integrated circuits (ICs) and ensuring the final yield of ICs chips. Recognizing the challenges posed by conventional deep learning-based methods for lithographic hotspot detection in meeting the demands of advanced IC manufacturing accuracy, this study introduces an LHS detection approach. This approach leverages multi-scale feature fusion to identify defects in lithographic layout hotspots accurately. This method incorporates the convolutional block attention module into the backbone network to enhance the focus of the model on the layout area. Additionally, a feature pyramid is employed to merge deep and shallow features from the layout pattern, significantly enhancing the capability of hotspot detection network to extract both image and semantic features. Concurrently, by utilizing a dense block that directly interconnects various layers, the network gains the capacity to capture the correlation between low-level and high-level features, thereby enhancing the perceptual capabilities of the model. Experimental results demonstrate the superiority of the algorithm across accuracy, false alarm, F1 score, and overall detection simulation time compared to alternative lithographic hotspot detection algorithms.

 

 

 

 

2024 DAC

LLM-HD: Layout Language model for Hotspot Detection with GDS Semantic Encoding

Author: Yuyang Chen, Yiwen Wu, Jingya Wang, Tao Wu, Xuming He, Jingyi Yu, Geng H

Affiliation: ShanghaiTech Univeristy, Shanghai, China

Abstract:

With the rapid downscaling of technology nodes, industrial flow such as pitch reduction, patterning flexibility, and lithography processing variability have been challenged. Layout hotspot detection is one of the most challenging and critical steps, which requires technology upgrading. Pattern matching and learning-based detectors are proposed as quick detection methods. However, these computer vision (CV) mode-based detectors use images transformed from layout GDS files as their inputs. It leads to foreground information (e.g. metal polygons) loss and even distortion when shrinking the image size to fit the mode input. Moreover, plenty of irrelevant background information such as non-polygon pixels are also fed into the mode, which hinders the fitting of the mode and results in a waste of computational resources. Concerning the disadvantage of the traditional CV mode, we propose a new layout hotspot detection paradigm, which directly detects hotspots on GDS files by exploiting a hierarchical GDS semantic representation scheme and a well-designed pre-trained natural language processing (NLP) mode. Compared with state-of-the-art works, ours achieves better results both on the ICCAD2012 metal layer benchmark and the more challenging ICCAD2020 via layer benchmark, which demonstrates the effectiveness and efficiency of our approach.

 

 

 

 

2024 ASP-DAC

APPLE: An Explainer of ML Predictions on Circuit Layout at the Circuit-Element Level

Author: Tao Zhang, Haoyu Yang, Kang Liu, Zhiyao Xie

Affiliation: Hong Kong University of Science and Technology; NVIDIA; Huazhong University of Science and Technology

Abstract:

In recent years, we have witnessed many excellent machine learning (ML) solutions targeting circuit layouts. These ML models provide fast predictions on various design objectives. However, almost all existing ML solutions have neglected the basic interpretability requirement from potential users. As a result, it is very difficult for users to figure out any potential accuracy degradation or abnormal behaviors of given ML models. In this work, we propose a new technique named APPLE to explain each ML prediction at the resolution level of circuit elements. To the best of our knowledge, this is the first effort to explain ML predictions on circuit layouts. It provides a significantly more reasonable, useful, and efficient explanation for lithography hotspot prediction, compared with the highest-cited prior solution for natural images.

 

 

 

 

2023 DATE

Automated and Agile Design of Layout Hotspot Detector via Neural Architecture Search

Authors：Zihao Chen, Fan Yang, Li Shang, Xuan Zeng

Affiliation:School of Microelectronics, State Key Laboratory of Integrated Chips and System, Fudan University, Shanghai, China

Abstract:

This paper presents a neural architecture search scheme for chip layout hotspot detection. In this work, hotspot detectors, in the form of neural networks, are modeled as weighted directed acyclic graphs. A variational autoencoder maps the discrete graph topological space into a continuous embedding space. Bayesian Optimization performs neural architecture search in this embedding space, where an architecture performance predictor is employed to accelerate the search process. Experimental studies on ICCAD 2012 and ICCAD 2019 Contest benchmarks demonstrate that, the proposed scheme significantly improves the agility of previous neural architecture search schemes, and generates hotspot detectors with competitive detection accuracy, false alarm rate, and inference time.

 

 

 

 

2022 ISCAS

Adversarial Sample Generation for Lithography Hotspot Detection

Authors：Shuyuan Sun; Yiyang Jiang; Fan Yang; Xuan Zeng

Affiliation:School of Microelectronics, State Key Laboratory of Integrated Chips and System, Fudan University, Shanghai, China

Abstract:

Lithography hotspot detection is of great significance in chip manufacturing. Hotspots are those patterns that may cause fatal defects in the final tape-out, such as short or open circuits. Therefore, identifying and eliminating hotspots in the early design stage can improve chip yield and reduce manufacturing costs. Traditionally, lithography simulation is used to detect hotspot patterns. But as the feature size shrinks and the design complexity increases, the lithography simulation of the entire chip requires a longer time overhead, which seriously delays the design cycle. Consequently, many deep learning-based methods have been proposed to accelerate hotspot detection. These approaches all show a good performance in the ICCAD 2012 contest benchmarks. However, deep neural networks are vulnerable to adversarial attacks. In this paper, we propose to generate samples by adjusting the critical distance between polygons in the layout based on existing patterns. Layouts are very sensitive to the distance between polygons, the type of a layout may flip by slight modifications in the distances. These adversarial samples are closer to the decision boundary of neural networks than the original ones. Experimental results show that the accuracy of neural network-based hotspot detectors drops significantly in the dataset formed by generated samples. Adding the generated samples to the training dataset improves the robustness and generalization ability of neural networks.

 

 

 

 

2022 DATE

Efficient Hotspot Detection via Graph Neural Network

Authors：Shuyuan Sun; Yiyang Jiang; Fan Yang; Bei Yu; Xuan Zeng

Affiliation:School of Microelectronics, State Key Laboratory of Integrated Chips and System, Fudan University, Shanghai, China

Abstract:

Lithography hotspot detection is of great importance in chip manufacturing. It aims to find patterns that may incur defects in the early design stage. Inspired by the success of deep learning in computer vision, many works convert layouts into images, turn the hotspot detection problem into an image classification task. Traditional graph-based methods consume fewer computer resources and less detection time compared to image-based methods, but they have too many false alarms. In this paper, a hotspot detection approach via the graph neural network (GNN) is proposed. We also propose a novel representation model to map a layout to one graph, in which we introduce multi-dimensional features to encode components of the layout. Then we use a modified GNN to further process the extracted layout features and get an embedding of the local geometric relationship. Experimental results on the ICCAD2012 Contest benchmarks show our proposed approach can achieve over 10x speedup and fewer false alarms without loss of accuracy. On the ICCAD2020 benchmark, our model can achieve 2.10% higher accuracy compared with the previous approach.

 

 

 

 

2022 ASP-DAC

Lithography hotspot Detection via Heterogeneous Federated Learning with Local Adaptation.

Author: Xuezhong Lin , Jingyu Pan , Jinming Xu, Yiran Chen, Cheng Zhuo

Affiliation: Zhejiang University, Hangzhou, China; Duke University, Durham, NC, USA

Abstract:

As technology scaling is approaching its physical limit, lithography hotspot detection has become an essential task in design for manufacturability. Although the deployment of machine learning in hotspot detection is found to save significant simulation time, such methods typically demand non-trivial quality data to build the model. While most design houses are actually short of quality data, they are also unwilling to directly share such layout related data to build a unified model due to the concerns on IP protection and model effectiveness. On the other hand, with data homogeneity and insufficiency within each design house, the locally trained models can be easily over-fitted, losing generalization ability and robustness when applying to the new designs. In this paper, we propose a heterogeneous federated learning framework for lithography hotspot detection that can address the aforementioned issues. The framework can build a more robust centralized global sub-model through heterogeneous knowledge sharing while keeping local data private. Then the global sub-model can be combined with a local submodel to better adapt to local data heterogeneity. The experimental results show that the proposed framework can overcome the challenge of non-independent and identically distributed (non-IID) data and heterogeneous communication to achieve very high performance in comparison to other state-of-the-art methods while guaranteeing good convergence in various scenarios.

 

 

 

 

2021 TCAD

Efficient Layout hotspot Detection via Binarized Residual Neural Network Ensemble

Author: Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, and Xuan Zeng

Affiliation: Microelectronics Department, State Key Laboratory of ASIC & System, Fudan University, Shanghai, China

Abstract:

Layout hotspot detection is of great importance in the physical verification flow. Deep neural network models have been applied to hotspot detection and achieved great successes. The layouts can be viewed as binary images. The binarized neural network (BNN) can thus be suitable for the hotspot detection problem. In this article, we propose a new deep learning architecture based on BNNs to speed up the neural networks in hotspot detection. A new binarized residual neural network is carefully designed for hotspot detection. Experimental results on ICCAD 2012 and 2019 benchmarks show that our architecture outperforms previous hotspot detectors in detecting accuracy and has an 8× speedup over the best deep learning-based solution. Since the BNN-based model is quite computationally efficient, a good tradeoff can be achieved between the efficiency and performance of the hotspot detector by applying ensemble learning approaches. Experimental results show that the ensemble models achieve better hotspot detection performance than the original with acceptable speed loss.

 

 

 

 

2021 TCAD

Efficient layout hotspot detection via binarized residual neural network ensemble.

Author: Yiyang Jiang, Fan Yang, Bei Yu, Dian Zhou, Xuan Zeng

Affiliation: Microelectronics Department, State Key Laboratory of ASIC & System, Fudan University, Shanghai, China

Abstract:

Layout hotspot detection is of great importance in the physical verification flow. Deep neural network models have been applied to hotspot detection and achieved great successes. The layouts can be viewed as binary images. The binarized neural network (BNN) can thus be suitable for the hotspot detection problem. In this article, we propose a new deep learning architecture based on BNNs to speed up the neural networks in hotspot detection. A new binarized residual neural network is carefully designed for hotspot detection. Experimental results on ICCAD 2012 and 2019 benchmarks show that our architecture outperforms previous hotspot detectors in detecting accuracy and has an 8× speedup over the best deep learning-based solution. Since the BNN-based model is quite computationally efficient, a good tradeoff can be achieved between the efficiency and performance of the hotspot detector by applying ensemble learning approaches. Experimental results show that the ensemble models achieve better hotspot detection performance than the original with acceptable speed loss.

 

 

 

 

2021 ICCAD

Hotspot Detection via Multi-task Learning and Transformer Encoder.

Author: Binwu Zhu, Ran Chen, Xinyun Zhang, Fan Yang, Xuan Zeng, Bei Yu , Martin D.F. Wong

Affiliation: The Chinese University of Hong Kong; Fudan University

Abstract:

With the rapid development of semiconductors and the continuous scaling-down of circuit feature size, hotspot detection has become much more challenging and crucial as a critical step in the physical verification flow. In recent years, advanced deep learning techniques have spawned many frameworks for hotspot detection. However, most existing hotspot detectors can only detect defects arising in the central region of small clips, making the whole detection process time-consuming on large layouts. Some advanced hotspot detectors can detect multiple hotspots in a large area but need to propose potential defect regions, and a refinement step is required to locate the hotspot precisely. To simplify the procedure of multi-stage detectors, an end-to-end single-stage hotspot detector is proposed to identify hotspots on large scales without refining potential regions. Besides, multiple tasks are developed to learn various pattern topological features. Also, a feature aggregation module based on Transformer Encoder is designed to globally capture the relationship between different features, further enhancing the feature representation ability. Experimental results show that our proposed framework achieves higher accuracy over prior methods with faster inference speed.

 

 

 

 

2021 DATE

Enhancements of Model and Method in Lithography hotspot Identification.

Author: Xuanyu Huang, Rui Zhang, Yu Huang, Peiyao Wang, Mei Li

Affiliation: Department of Mechanical Engineering, Center for Nano and Micro Mechanics, Tsinghua University, Beijing, China; HiSilicon Technologies Co., Ltd., Shenzhen, China

Abstract:

The manufacturing of integrated circuits (ICs) has been continuously improved through the advancement of fabrication technology nodes. However the lithography hotspots (HSs) caused by optical diffraction problems seriously affect the yield and reliability of ICs. Although lithography simulation can accurately capture the HSs through physically simulating the lithography process, it requires a lot of computing resources, which usually takes > 100 CPU · h /mm 2 [1]. Due to the image recognition nature, the state-of-the-art HS identification algorithms based on deep learning have obvious advantages in reducing run time comparing to the traditional algorithms. However, its accuracy still needs to be enhanced since there are many false alarms of non-hotspots (NHSs) and escapes of the real HSs, which makes it difficult to be a signoff technique. In this paper, we propose two enhancements in HS identification. First, a hybrid deep learning model is proposed in lithography HS identification, which includes a CNN model to combine physical features. Second, an ensemble learning method is proposed based on multiple submodels. The proposed enhanced model and method can achieve high HS identification accuracy on the benchmarks 1–4 of the ICCAD 2012 dataset with recall> 98.8%. In addition, it can achieve even 100% recall on the benchmark 1 and benchmark 3 while maintaining the precision at a high level with 53.6% and 87.1%, respectively. Moreover, for the first time it can achieve not only 100% recall on benchmark 5, but also high precision of 61.8%, which is much higher than any published deep learning methods for HSs identification, as far as we know. The proposed model and methodology can be applied in industrial IC designs due to its effectiveness and efficiency.

 

 

 

 

2021 ASP-DAC

Attacking a CNN-based Layout hotspot Detector Using Group Gradient Method.

Author: Haoyu Yang, Shifan Zhang, Kang Liu, Siting Liu, Benjamin Tan, Ramesh Karri, Siddhart Garg, Bei Yu, Evangeline F.Y. Young

Affiliation: Chinese University of Hong Kong; New York University;

Abstract:

Deep neural networks are being used in disparate VLSI design automation tasks, including layout printability estimation, mask optimization, and routing congestion analysis. Preliminary results show the power of deep learning as an alternate solution in state-of-the-art design and sign-off flows. However, deep learning is vulnerable to adversarial attacks. In this paper, we examine the risk of state-of-the-art deep learning-based layout hotspot detectors under practical attack scenarios. We show that legacy gradient-based attacks do not adequately consider the design rule constraints. We present an innovative adversarial attack formulation to attack the layout clips and propose a fast group gradient method to solve it. Experiments show that the attack can deceive the deep neural networks using small perturbations in clips which preserve layout functionality while meeting the design rules. The source code is available at https://github.com/phdyang007/dlhsd/tree/dct_as_conv.

 

 

 

 

2020 ICCAD

Hotspot Detection via Attention-based Deep Layout Metric Learning

Author: Hao Geng, Haoyu Yang, Lu Zhang, Fan Yang, Xuan Zeng, Bei Yu

Affiliation: Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, New Territories, Hong Kong

Abstract:

With the aggressive and amazing scaling of the feature size of semiconductors, hotspot detection has become a crucial and challenging problem in the generation of optimized mask design for better printability. Machine learning techniques, especially deep learning, have attained notable success on hotspot detection tasks. However, most existing hotspot detectors suffer from suboptimal performance due to two-stage flow and less efficient representations of layout features. What is more, most works can only solve simple benchmarks with apparent hotspot patterns like ICCAD 2012 Contest benchmarks. In this article, we first develop a new end-to-end hotspot detection flow where layout feature embedding and hotspot detection are jointly performed. An attention mechanism-based deep convolutional neural network (CNN) is exploited as the backbone to learn embeddings for layout features and classify the hotspots simultaneously. The experimental results demonstrate that our framework achieves accuracy improvement over prior arts with fewer false alarms and faster inference speed on much more challenging benchmarks.

 

 

 

 

2020 ISPD

DRC Hotspot Prediction at Sub-10nm Process Nodes Using Customized Convolutional Network

Author: Rongjian Liang, Hua Xiang, Diwesh Pandey, Lakshmi Reddy, Shyam Ramji, Jiang Hu

Affiliation: Texas A&M University, College Station, TX, USA

Abstract:

As the semiconductor process technology advances into sub-10nm regime, cell pin accessibility, which is a complex joint effect from the pin shape and nearby blockages, becomes a main cause for DRC violations. Therefore, a machine learning model for DRC hotspot prediction needs to consider both very high-resolution pin shape patterns and low-resolution layout information as input features. A new convolutional neural network technique, J-Net, is introduced for the prediction with mixed resolution features. This is a customized architecture that is flexible for handling various input and output resolution requirements. It can be applied at placement stage without using global routing information. This technique is evaluated on 12 industrial designs at 7nm technology node. The results show that it can improve true positive rate by 37%, 40% and 14% respectively, compared to three recent works, with similar false positive rates.

 

 

 

 

2019 TCAD

Layout hotspot Detection with Feature Tensor Generation and Deep Biased Learning

Author: Haoyu Yang, Jing Su, Yi Zou, Yuzhe Ma, Bei Yu, Evangeline F. Y. Young

Affiliation: Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong

Abstract:

Detecting layout hotspots is a key step in the physical verification flow. Although machine learning solutions show benefits over lithography simulation and pattern matching-based methods, it is still hard to select a proper model for large scale problems and inevitably, performance degradation occurs. To overcome these issues, in this paper, we develop a deep learning framework for high performance and large scale hotspot detection. First, we use feature tensor generation to extract representative layout features that fit well with convolutional neural networks while keeping the spatial relationship of the original layout pattern with minimal information loss. Second, we propose a biased learning (BL) algorithm to train the convolutional neural network to further improve detection accuracy with small false alarm penalties. In addition, to simplify the training procedure and seek a better tradeoff between accuracy and false alarms, we extend the original BL to a batch BL algorithm. Experimental results show that our framework outperforms previous machine learning-based hotspot detectors in both ICCAD 2012 Contest benchmarks and large scale industrial benchmarks. Source code and trained models are available at https://github.com/phdyang007/dlhsd.

 

 

 

 

2019 ASP-DAC

Detecting multi-layer layout hotspots with adaptive squish patterns

Author: Haoyu Yang, Piyush Pathak, Frank Gennari, Ya-Chieh Lai, Bei Yu

Affiliation: CSE Department, CUHK; Cadence Design Systems Inc.

Abstract:

Layout hotpot detection is one of the critical steps in modern integrated circuit design flow. It aims to find potential weak points in layouts before feeding them into manufacturing stage. Rapid development of machine learning has made it a preferable alternative of traditional hotspot detection solutions. Recent researches range from layout feature extraction and learning model design. However, only single layer layout hotspots are considered in state-of-the-art hotspot detectors and certain defects such as metal-to-via failures are not naturally supported. In this paper, we propose an adaptive squish representation for multilayer layouts, which is storage efficient, lossless and compatible with deep neural networks. We conduct experiments on 14nm industrial designs with a metal layer and its two adjacent via layers that contain metal-to-via hotspots. Results show that the adaptive squish representation can achieve satisfactory hotspot detection accuracy by incorporating a mediumsized convolutional neural networks.

 

 

 

 

2019 DAC

Faster Region-based hotspot Detection

Author: Ran Chen; Wei Zhong; Haoyu Yang; Hao Geng; Xuan Zeng; Bei Yu

Affiliation: Chinese University of Hong Kong; Dalian University of Technology; Fudan University

Abstract:

As the circuit feature size continuously shrinks down, hotspot detection has become a more challenging problem in modern DFM flows. Developed deep learning techniques have recently shown their advantages on hotspot detection tasks. However, existing hotspot detectors only accept small layout clips as input with potential defects occurring at a center region of each clip, which will be time consuming and waste lots of computational resources when dealing with large full-chip layouts. In this paper, we develop a new end-to-end framework that can detect multiple hotspots in a large region at a time and promise a better hotspot detection performance. We design a joint auto-encoder and inception module for efficient feature extraction. A two-stage classification and regression flow is proposed to efficiently locate hotspot regions roughly and conduct final prediction with better accuracy and false alarm penalty. Experimental results show that our framework enables a significant speed improvement over existing methods with higher accuracy and fewer false alarms.

 

 

 

 

2017 SPIE

Imbalance aware lithography hotspot detection: a deep learning approach

Author: Haoyu Yang, Luyang Luo, Jing Su, Chenxi Lin, and Bei Yu

Affiliation: The Chinese Univ. of Hong Kong (Hong Kong, China); ASML Brion (United States)

Abstract:

With the advancement of VLSI technology nodes, light diffraction caused lithographic hotspots have become a serious problem affecting manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with extreme scaling of transistor feature size and more and more complicated layout patterns, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. In this paper, we present a deep convolutional neural network (CNN) targeting representative feature learning in lithography hotspot detection. We carefully analyze impact and effectiveness of different CNN hyper-parameters, through which a hotspot-detection-oriented neural network mode is established. Because hotspot patterns are always minorities in VLSI mask design, the training data set is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained mode with high classification accuracy may still suffer from high false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply minority upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network mode achieves highly comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

 

 

 

 

2017 SPIE

Imbalance aware lithography hotspot detection: A deep learning approach

Author: Haoyu Yang, Luyang Luo, Jing Su, Chenxi Lin, Bei Yu

Affiliation: The Chinese Univ. of Hong Kong; ASML Brion (United States)

Abstract:

With the advancement of VLSI technology nodes, light diffraction caused lithographic hotspots have become a serious problem affecting manufacture yield. Lithography hotspot detection at the post-OPC stage is imperative to check potential circuit failures when transferring designed patterns onto silicon wafers. Although conventional lithography hotspot detection methods, such as machine learning, have gained satisfactory performance, with extreme scaling of transistor feature size and more and more complicated layout patterns, conventional methodologies may suffer from performance degradation. For example, manual or ad hoc feature extraction in a machine learning framework may lose important information when predicting potential errors in ultra-large-scale integrated circuit masks. In this paper, we present a deep convolutional neural network (CNN) targeting representative feature learning in lithography hotspot detection. We carefully analyze impact and effectiveness of different CNN hyper-parameters, through which a hotspot-detection-oriented neural network model is established. Because hotspot patterns are always minorities in VLSI mask design, the training data set is highly imbalanced. In this situation, a neural network is no longer reliable, because a trained model with high classification accuracy may still suffer from high false negative results (missing hotspots), which is fatal in hotspot detection problems. To address the imbalance problem, we further apply minority upsampling and random-mirror flipping before training the network. Experimental results show that our proposed neural network model achieves highly comparable or better performance on the ICCAD 2012 contest benchmark compared to state-of-the-art hotspot detectors based on deep or representative machine leaning.

 

 

 

 

2011 DAC

AENEID: a generic lithography-friendly detailed router based on post-RET data learning and hotspot detection

Author: Duo Ding, Jhih-Rong Gao, Kun Yuan, David Z. Pan

Affiliation: ECE Dept. The Univ. of Texas at Austin, Austin

Abstract:

In the era of deep sub-wavelength lithography for nanometer VLSI designs, manufacturability and yield issues are critical and need to be addressed during the key physical design implementation stage, in particular detailed routing. However, most existing studies for lithography-friendly routing suffer from either huge run-time due to the intensive lithographic computations involved, or severe loss of quality of results because of the inaccurate predictive models. In this paper, we propose AENEID - a fast, generic and high performance lithography-friendly detailed router for enhanced manufacturability. AENEID combines novel hotspot detection and routing path prediction techniques through modern data learning methods and applies them at the detailed routing stage to drive high fidelity lithography-friendly routing. Compared with existing litho-friendly routing works, AENEID demonstrates 26% to 66% (avg. 50%) of lithography hotspot reduction at the cost of only 18%-38% (avg. 30%) of run-time overhead.

 

 

 

 

2024 GLSVLSI

Automated Lithography Resolution Enhancement with Deep Learning Enabled Layout Modification during Physical Design Stage

Authors: Zixi Liu,Yibo Lin,Xiaojing Su,Xiaohuan Ling,Hong Xin,Bojie Ma,Yajuan Su,Yayi Wei

Affiliation: National Key Laboratory for Multimedia Information Processing, School of Computer Science, and the Center for Energy-Efficient Computing and Applications, Peking University

Abstract:

Lithography compliance is critical to the manufacturability of modern integrated circuits. Applying resolution enhancement techniques like OPC and ILT at sign-off stages is too late and can only make minor layout adjustment, which has limited optimization space to improve printability in advanced technology nodes.

To explore larger optimization space, we propose an automated lithography resolution enhancement framework that targets to improve lithography process window by layout modification during early design stages like physical design. The framework simultaneously adjusts layout patterns towards lithography compliance, and meanwhile subjecting to design rules and connectivity constraints. Experimental results demonstrate that our framework can enable efficient layout optimization and achieve an average of 5.69% improvement in lithography process window.

 

 

 

 

2023 J MICRO

Evaluation of convolutional neural network for fast extreme ultraviolet lithography simulation using imec 3 nm node mask patterns

Author: Hiroyoshi Tanabe, Akira Jinguji, Atsushi Takahashi

Affiliation: Tokyo Institute of Technology (Japan)

Abstract:

Background: Mask 3D (M3D) effects distort diffraction amplitudes from extreme ultraviolet masks. In our previous work, we developed a convolutional neural network (CNN) that very quickly predicted the distorted diffraction amplitudes from input mask patterns. The mask patterns were restricted to Manhattan patterns. Aim: We verify the potentials and the limitations of CNN using imec 3 nm node (iN3) mask patterns. Approach: We apply the same CNN architecture in the previous work to mask patterns, which mimic iN3 logic metal or via layers. In addition, to study more general mask patterns, we apply the architecture to iN3 metal/via patterns with optical proximity correction (OPC) and curvilinear via patterns. In total, we train five different CNNs: metal patterns w/wo OPC, via patterns w/wo OPC, and curvilinear via patterns. After the training, we validate each CNN using validation data with the above five different characteristics. Results: When we use the training and validation data with the same characteristics, the validation loss becomes very small. Our CNN architecture is flexible enough to be applied to iN3 metal and via layers. The architecture has the capability to recognize curvilinear mask patterns. On the other hand, using the training and validation data with different characteristics will lead to large validation loss. The selection of training data is very important for obtaining high accuracy. We examine the impact of M3D effects on iN3 metal layers. A large difference is observed in the tip to tip (T2T) critical dimension calculated by the thin mask model and thick mask model. This is due to the mask shadowing effect at T2T slits. Conclusions: The selection of training data is very important for obtaining high accuracy. Our test results suggest that layer specific CNN could be constructed, but further development of CNN architecture could be required.

 

 

 

 

2022 DAC

Generic lithography modeling with dual-band optics-inspired neural networks

Author:Haoyu Yang, Zongyi Li, Kumara Sastry, Saumyadip Mukhopadhyay, Mark Kilgard, Anima Anandkumar

Affiliation: NVIDIA and Caltech,NVIDIA

Abstract:

Lithography simulation is a critical step in VLSI design and optimization for manufacturability. Existing solutions for highly accurate lithography simulation with rigorous models are computationally expensive and slow, even when equipped with various approximation techniques. Recently, machine learning has provided alternative solutions for lithography simulation tasks such as coarse-grained edge placement error regression and complete contour prediction. However, the impact of these learning-based methods has been limited due to restrictive usage scenarios or low simulation accuracy. To tackle these concerns, we introduce an dual-band optics-inspired neural network design that considers the optical physics underlying lithography. To the best of our knowledge, our approach yields the first published via/metal layer contour simulation at 1nm2/pixel resolution with any tile size. Compared to previous machine learning based solutions, we demonstrate that our framework can be trained much faster and offers a significant improvement on efficiency and image quality with 20× smaller model size. We also achieve 85× simulation speedup over traditional lithography simulator with ~ 1% accuracy loss.

 

 

 

 

2022 ICCAD

DeePEB: A Neural Partial Differential Equation Solver for Post Exposure Baking Simulation in Lithography

Author: Qipan Wang, Xiaohan Gao, Yibo Lin, Runsheng Wang, and Ru Huang

Affiliation: Peking University,Peking University and Beijing Advanced Innovation Center for Integrated Circuits, Beijing, China

Abstract:

Post Exposure Baking (PEB) has been widely utilized in advanced lithography. PEB simulation is critical in the lithography simulation flow, as it bridges the optical simulation result and the final developed profile in the photoresist. The process of PEB can be described by coupled partial differential equations (PDE) and corresponding boundary and initial conditions. Recent years have witnessed growing presence of machine learning algorithms in lithography simulation, while PEB simulation is often ignored or treated with compact models, considering the huge cost of solving PDEs exactly. In this work, based on the observation of the physical essence of PEB, we propose DeePEB: a neural PDE Solver for PEB simulation. This model is capable of predicting the PEB latent image with high accuracy and >100 × acceleration (compared to the commercial rigorous simulation tool), paving the way for efficient and accurate photoresist modeling in lithography simulation and layout optimization.

 

 

 

 

2019 DAC

LithoGAN: End-to-End Lithography Modeling with Generative Adversarial Networks

Author: Wei Ye, Mohamed Baker Alawieh, Yibo Lin, David Z. Pan

Affiliation: ECE Department, UT Austin

Abstract:

Lithography simulation is one of the most fundamental steps in process modeling and physical verification. Conventional simulation methods suffer from a tremendous computational cost for achieving high accuracy. Recently, machine learning was introduced to trade off between accuracy and runtime through speeding up the resist modeling stage of the simulation flow. In this work, we propose LithoGAN, an end-to-end lithography modeling framework based on a generative adversarial network (GAN), to map the input mask patterns directly to the output resist patterns. Our experimental results show that LithoGAN can predict resist patterns with high accuracy while achieving orders of magnitude speedup compared to conventional lithography simulation and previous machine learning based approach.

 

 

 

 

2019 TCAD

Data Efficient Lithography Modeling With Transfer Learning and Active Data Selection

Author: Yibo Lin, Meng Li, Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima, David Z. Pan

Affiliation: Department of Electrical and Computer Engineering, University of Texas at Austin, Austin, TX, USA, Memory Lithography Group, Toshiba Memory Corporation, Yokohama, Japan

Abstract:

Lithography simulation is one of the key steps in physical verification, enabled by the substantial optical and resist models. A resist model bridges the aerial image simulation to printed patterns. While the effectiveness of learning-based solutions for resist modeling has been demonstrated, they are considerably data-demanding. Meanwhile, a set of manufactured data for a specific lithography configuration is only valid for the training of one single model, indicating low data efficiency. Due to the complexity of the manufacturing process, obtaining enough data for acceptable accuracy becomes very expensive in terms of both time and cost, especially during the evolution of technology generations when the design space is intensively explored. In this paper, we propose a new resist modeling framework for contact layers, utilizing existing data from old technology nodes and active selection of data in a target technology node, to reduce the amount of data required from the target lithography configuration. Our framework based on transfer learning and active learning techniques is effective within a competitive range of accuracy, i.e., 3×−10× reduction on the amount of training data with comparable accuracy to the state-of-the-art learning approach.

 

 

 

 

2017 SPIE

Accurate lithography simulation model based on convolutional neural networks

Author: Yuki Watanabe, Taiki Kimura, Tetsuaki Matsunawa, Shigeki Nojima

Affiliation: Toshiba Corp. (Japan)

Abstract:

Lithography simulation is an essential technique for today's semiconductor manufacturing process. In order to calculate an entire chip in realistic time, compact resist model is commonly used. The model is established for faster calculation. To have accurate compact resist model, it is necessary to fix a complicated non-linear model function. However, it is difficult to decide an appropriate function manually because there are many options. This paper proposes a new compact resist model using CNN (Convolutional Neural Networks) which is one of deep learning techniques. CNN model makes it possible to determine an appropriate model function and achieve accurate simulation. Experimental results show CNN model can reduce CD prediction errors by 70% compared with the conventional model.

 

 

 

 

2024 TCAD

RL-OPC: mask Optimization With Deep Reinforcement Learning.

Author: Xiaoxiao Liang; Yikang Ouyang; Haoyu Yang; Bei Yu; Yuzhe Ma

Affiliation: The Hong Kong University of Science and Technology (Guangzhou), Guangzhou, China; Design Automation Research Group, Nvidia, Austin, TX, USA; Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong, SAR

Abstract:

Mask optimization is a vital step in the VLSI manufacturing process in advanced technology nodes. As one of the most representative techniques, optical proximity correction (OPC) is widely applied to enhance printability. Since conventional OPC methods consume prohibitive computational overhead, recent research has applied machine learning techniques for efficient mask optimization. However, existing discriminative learning modes rely on a given dataset for supervised training, and generative learning modes usually leverage a proxy optimization objective for end-to-end learning, which may limit the feasibility. In this article, we pioneer introducing the reinforcement learning (RL) mode for mask optimization, which directly optimizes the preferred objective without leveraging a differentiable proxy. Intensive experiments show that our method outperforms state-of-the-art solutions, including academic approaches and commercial toolkits.

 

 

 

 

2024 J MICRO

Mask deep check to pre-detect defects in curvilinear mask

Author: Sooyong Lee, Jeeyong Lee, Sinjeung Park, Byungjun Kang, Juyun Park, Bongkeun Kim, Joonsung Kim, Seung-Hune Yang, Seongtae Jeong

Affiliation: SAMSUNG Electronics Co., Ltd. (Korea, Republic of)

Abstract:

In recent years, curvilinear mask technology has emerged as a next-generation resolution enhancement method for photomasks, providing optimal margins by maximizing the degree of freedom in pattern design. However, this technology presents challenges in defining the layout design rule limits based solely on geometric information, such as width, space, and corner-to-corner. With the introduction of multi-beam mask writers for curvilinear pattern production, a distinct set of defects that are difficult to pre-detect by conventional mask rule check have occurred, as these cannot be explained by geometry terms alone. In this study, we propose a deep learning-based mask check method, named mask deep check (MDC) for pre-detect defects in inspection. The proposed vector graphics transformer (VGT) uses the state-of-the-art transformer architecture, drawing an analogy between the vertices of curvilinear patterns and words in natural language. We demonstrate improved performance of VGT-based MDC compared to a traditional rule-based approach and a convolutional neural network-based MDC method. Importantly, VGT exhibits robustness in recall, ensuring that defective patterns are not misclassified as normal, thereby preventing missed defects. Moreover, by employing attention maps to visualize VGT results, we gain explainability and reveal that mask defects may arise from issues related to the fabrication of specific designs, rather than being solely attributable to geometric features. VGT-based MDC contributes to a better understanding of the challenges associated with curvilinear mask technology and offers an effective solution for detecting mask defects.

 

 

 

 

2024 DAC

Efficient Bilevel Source mask Optimization

Author: Guojin Chen, Hongquan He, Peng Xu, Hao Geng, Bei Yu

Affiliation: The Chinese University of HongKong, ShanghaiTech University, The Chinese University of Hong Kong

Abstract:

Resolution Enhancement Techniques (RETs) are critical to meet the demands of advanced technology nodes. Among RETs, Source mask Optimization (SMO) is pivotal, concurrently optimizing both the source and the mask to expand the process window. Traditional SMO methods, however, are limited by sequential and alternating optimizations, leading to extended runtimes without performance guarantees. This paper introduces a unified SMO framework utilizing the accelerated Abbe forward imaging to enhance precision and efficiency. Further, we propose the innovative \texttt{BiSMO} framework, which reformulates SMO through a bilevel optimization approach, and present three gradient-based methods to tackle the challenges of bilevel SMO. Our experimental results demonstrate that \texttt{BiSMO} achieves a remarkable 40\% reduction in error metrics and 8$\times$ increase in runtime efficiency, signifying a major leap forward in SMO.

 

 

 

 

2024 DAC

EMOGen: Enhancing mask Optimization via Pattern Generation

Author: Su Zheng, Yuzhe Ma, Bei Yu, Martin Wong

Affiliation: The Chinese University of Hong Kong, The Hong Kong University of Science and Technology (Guangzhou)

Abstract:

Layout pattern generation via deep generative modes is a promising methodology for building practical large-scale pattern libraries. However, although improving optical proximity correction (OPC) is a major target of existing pattern generation methods, they are not explicitly trained for OPC and integrated into OPC methods. In this paper, we propose EMOGen to enable the co-evolution of layout pattern generation and learning-based OPC methods. With the novel co-evolution methodology, we achieve up to 39% enhancement in OPC and 34% improvement in pattern legalization.

 

 

 

 

2024 DAC

CAMO: Correlation-Aware mask Optimization with Modulated Reinforcement Learning

Author: Xiaoxiao Liang, Haoyu Yang, Kang Liu, Bei Yu, Yuzhe Ma

Affiliation: The Hong Kong University of Science and Technology (Guangzhou), NVIDIA Corp, Huazhong University of Science and Technology, The Chinese University of Hong Kong

Abstract:

Optical proximity correction (OPC) is a vital step to ensure printability in modern VLSI manufacturing. Various OPC approaches have been proposed, which are typically data-driven and hardly involve particular considerations of the OPC problem, leading to potential performance bottlenecks. In this paper, we propose CAMO, a reinforcement learning-based OPC system that integrates important principles of the OPC problem. CAMO explicitly involves the spatial correlation among the neighboring segments and an OPC-inspired modulation for movement action selection. Experiments are conducted on via patterns and metal patterns. The results demonstrate that CAMO outperforms state-of-the-art OPC engines from both academia and industry.

 

 

 

 

2024 DAC

Fracturing-aware Curvilinear ILT via Circular E-beam mask Writer

Author：Xinyun Zhang , Su Zheng , Guojin Chen , Binwu Zhu ,Hong Xu ,Bei Yu

Affiliation: The Chinese University of Hong Kong

Abstract:

Inverse lithography technology (ILT) is vital in optical proximity correction, tending to generate curvilinear masks for optimal process windows. Traditional curvilinear mask manufacturing involves fracturing into rectangles, requiring expensive mask write times. A novel E-beam mask writer that writes variable radius circles per shot significantly reduces the shot count for curvilinear masks. We present two methods to generate circular fracturing-aware masks. The first one converts pixel-based masks from existing ILT methods into circle-based masks using predefined rules. The second one integrates circular constraints into the ILT process, generating circle-based masks directly via optimization. Extensive experimental results validate both approaches' effectiveness.

 

 

 

 

2023 J MICRO

Curvilinear mask optimization with refined generative adversarial nets

Author:Qingchen Cao, Peng Xu, Song Sun, Jianfang He, Juan Wei, Jiangliu Shi, Yayi Wei

Affiliation: Institute of Microelectronics, Chinese Academy of Sciences (China),Univ. of Chinese Academy of Sciences (China),Beijing Superstring Academy of Memory Technology (China)

Abstract:

Inverse lithography technology (ILT) can optimize the mask to gain the best process window and image quality when the design dimension shrinks. However, as a pixel level correction method, ILT is very time-consuming. In order to make the ILT method useful in real mask fabrication, the runtime of ILT-based optical proximity correction mask must evidently decrease while keeping the good lithographic metric performance. Our study proposes a framework to obtain the curvilinear ILT mask with generative adversarial network (GAN). It is subsequently refined with the traditional ILT to exclude unexpected outliers generated by the GAN method. We design conditional GAN, reverse GAN (RGAN), and high discretion GAN (HDGAN) to generate curvilinear ILT mask. Their runtime and the performance are compared. Compared with the CILT method, the speed of GAN type methods with the afterward refinement is increased by an order of magnitude. The RGAN has a better performance in edge placement error and process variation band evaluation, and HDGAN has a better performance in the mask error enhancement factor evaluation. The designed RGAN and HDGAN are promising in actual application to generate the curvilinear mask. They can evidently decrease the runtime and have better lithographic metric performance.

 

 

 

 

2023 DAC

Physics-informed optical kernel regression using complex-valued neural fields.

Author: Guojin Chen, Zehua Pei, Haoyu Yang, Yuzhe Ma, Bei Yu, and Martin Wong

Affiliation: Chinese University of Hong Kong

Abstract:

Lithography is fundamental to integrated circuit fabrication, necessitating large computation overhead. The advancement of machine learning (ML)-based lithography models alleviates the trade-offs between manufacturing process expense and capability. However, all previous methods regard the lithography system as an image-to-image black box mapping, utilizing network parameters to learn by rote mappings from massive mask-to-aerial or mask-to-resist image pairs, resulting in poor generalization capability. In this paper, we propose a new ML-based paradigm disassembling the rigorous lithographic model into non-parametric mask operations and learned optical kernels containing determinant source, pupil, and lithography information. By optimizing complex-valued neural fields to perform optical kernel regression from coordinates, our method can accurately restore lithography system using a small-scale training dataset with fewer parameters, demonstrating superior generalization capability as well. Experiments show that our framework can use 31% of parameters while achieving 69× smaller mean squared error with 1.3× higher throughput than the state-of-the-art.

 

 

 

 

2023 J MICRO

Enhancing mask synthesis for curvilinear masks in full-chip extreme ultraviolet lithography

Author: Kevin Hooker, Guangming Xiao, Yu-Po Tang, Yunqiang Zhang, Moongyu Jeong, John Valadez, Kevin Lucas

Affiliation: Synopsys, Inc. (United States), Synopsys Taiwan Co., Ltd. (Taiwan), Synopsys Korea Inc. (Republic of Korea)

Abstract:

With recent technology advancements of multi-beam mask writers, curvilinear masks can now be extended to advanced EUV lithography generations. Inverse lithography technology (ILT) is a curvilinear mask-friendly mask synthesis solution with superior quality but slower TAT than mainstream rule-based assist feature + OPC methods. To achieve ILT quality for full-chip layouts, a faster curvilinear ILT-based mask synthesis solution is desired. We present a hybrid curvilinear mask solution with ILT and curve OPC for full-chip EUV layers. Results of full-chip EUV in lithographic performance and runtime are compared among different solutions including traditional Manhattan OPC, curvilinear ILT, and hybrid machine learning (ML) ILT plus curve OPC. Another important factor of curvilinear mask advancement is data volume. We present our curve OPC solution with the cubic Bezier curve to control the data volume of curvilinear masks. The mask writing process is playing an increasingly important role in the overall manufacturing flow. Therefore, we also present an enhanced mask synthesis flow utilizing a mask error correction solution for curvilinear masks written by a multi-beam writer.

 

 

 

 

2022 J MICRO

Machine learning optical proximity correction with generative adversarial networks

Author: Weilun Ciou, Tony Hu, Yi-Yen Tsai, Chung-Te Hsuan, Elvis Yang, Ta-Hung Yang, Kuang-Chao Chen

Affiliation:Macronix International Co., Ltd. (Taiwan),Macronix International Co., Ltd., Technology Development Center, Hsinchu, Taiwan (Taiwan)

Abstract:

Two generative adversarial networks (GANs) were constructed, a pix2pix model was first trained to learn the correspondences between mask image and paired ADI contour image collected on wafer. The second model is embedded into machine learning mask correction (ML-OPC) framework, output mask is optimized through minimizing pixel difference between design target and simulated contour.

 

 

 

 

2021 ASP-DAC

Deep Learning for mask Synthesis and Verification: A survey.

Author: Yibo Lin

Affiliation: Peking University

Abstract:

Achieving lithography compliance is increasingly difficult in advanced technology nodes. Due to complicated lithography modeling and long simulation cycles, verifying and optimizing photomasks becomes extremely expensive. To speedup design closure, deep learning techniques have been introduced to enable data-assisted optimization and verification. Such approaches have demonstrated promising results with high solution quality and efficiency. Recent research efforts show that learning-based techniques can accomplish more and more tasks, from classification, simulation, to optimization, etc. In this paper, we will survey the successful attempts of advancing mask synthesis and verification with deep learning and highlight the domain-specific learning techniques. We hope this survey can shed light on the future development of learning-based design automation methodologies.

 

 

 

 

2021 ICCAD

DevelSet: Deep neural level set for instant mask optimization.

Author: Guojin Chen, Ziyang Yu, Hongduo Liu, Yuzhe Ma, and Bei Yu

Affiliation: The Chinese University of Hong Kong

Abstract:

With the feature size continuously shrinking in advanced technology nodes, mask optimization is increasingly crucial in the conventional design flow, accompanied by an explosive growth in prohibitive computational overhead in optical proximity correction (OPC) methods. Recently, inverse lithography technique (ILT) has drawn significant attention and is becoming prevalent in emerging OPC solutions. However, ILT methods are either time-consuming or in weak performance of mask printability and manufacturability. In this paper, we present DevelSet, a GPU and deep neural network (DNN) accelerated level set OPC framework for metal layer. We first improve the conventional level set-based ILT algorithm by introducing the curvature term to reduce mask complexity and applying GPU acceleration to overcome computational bottlenecks. To further enhance printability and fast iterative convergence, we propose a novel deep neural network delicately designed with level set intrinsic principles to facilitate the joint optimization of DNN and GPU accelerated level set optimizer. Experimental results show that DevelSet framework surpasses the state-of-the-art methods in printability and boost the runtime performance achieving instant level (around 1 second).

 

 

 

 

2020 ASP-DAC

VLSI mask Optimization: From Shallow To Deep Learning

Author: Haoyu Yang, Wei Zhong, Yuzhe Ma, Hao Geng, Ran Chen, Wanli Chen, Bei Yu

Affiliation: CSE Department, The Chinese University of Hong Kong; ISE, Dalian University of Technology

Abstract:

VLSI mask optimization is one of the most critical stages in manufacturability aware design, which is costly due to the complicated mask optimization and lithography simulation. Recent researches have shown prominent advantages of machine learning techniques dealing with complicated and big data problems, which bring potential of dedicated machine learning solution for DFM problems and facilitate the VLSI design cycle. In this paper, we focus on a heterogeneous OPC framework that assists mask layout optimization. Preliminary results show the efficiency and effectiveness of proposed frameworks that have the potential to be alternatives to existing EDA solutions.

 

 

 

 

2020 TCAD

GAN-OPC: mask optimization with lithography-guided generative adversarial nets

Author: Haoyu Yang , Shuhe Li, Zihao Deng, Yuzhe Ma , Bei Yu and Evangeline F. Y. Young

Affiliation: Department of Computer Science and Engineering, Chinese University of Hong Kong, Hong Kong;

Abstract:

Mask optimization has been a critical problem in the VLSI design flow due to the mismatch between the lithography system and the continuously shrinking feature sizes. Optical proximity correction (OPC) is one of the prevailing resolution enhancement techniques (RETs) that can significantly improve mask printability. However, in advanced technology nodes, the mask optimization process consumes more and more computational resources. In this article, we develop a generative adversarial network (GAN) mode to achieve better mask optimization performance. We first develop an OPC-oriented GAN flow that can learn target-mask mapping from the improved architecture and objectives, which leads to satisfactory mask optimization results. To facilitate the training process and ensure better convergence, we propose a pretraining scheme that jointly trains the neural network with inverse lithography technique (ILT). We also propose an enhanced generator design with a U-Net architecture and a subpixel super-resolution structure that promise a better convergence and a better mask quality, respectively. At convergence, the generative network is able to create quasi-optimal masks for given target circuit patterns and fewer normal OPC steps are required to generate high quality masks. The experimental results show that our flow can facilitate the mask optimization process as well as ensure a better printability.

 

 

 

 

2020 ICCAD

Neural-ILT: Migrating ILT to Neural Networks for mask Printability and Complexity Co-optimization

Author: Bentian Jiang,Lixin Liu,Yuzhe Ma,Hang Zhang,Bei Yu,Evangeline F.Y. Young

Affiliation: Chinese University of Hong Kong; Cornell University

Abstract:

Optical proximity correction (OPC) for advanced technology node now has become extremely expensive and challenging. Conventional mode-based OPC encounters performance degradation and large process variation, while aggressive approach such as inverse lithography technology (ILT) suffers from large computational overhead for both mask optimization and mask writing processes. In this paper, we developed Neural-ILT, an end-to-end learning-based OPC framework, which literally conducts mask prediction and ILT correction for a given layout in a single neural network, with the objectives of (1) mask printability enhancement, (2) mask complexity optimization and (3) flow acceleration. Quantitative results show that, comparing to the state-of-the-art (SOTA) learning-based OPC solution and conventional ILT flow, Neural-ILT can achieve 30× ~ 70× turn around time (TAT) speedup with lower mask complexity and comparable mask printability. We believe this work could arouse the interests of bridging well-developed deep learning toolkits to GPU-based high-performance lithographic computations to achieve groundbreaking performance boosting on various computational lithography-related tasks.

 

 

 

 

2020 ICCAD

DAMO: Deep agile mask optimization for full chip scale.

Author: Guojin Chen, Wanli Chen, Yuzhe Ma, Haoyu Yang, and Bei Yu.

Affiliation: Chinese University of Hong Kong

Abstract:

Continuous scaling of the VLSI system leaves a great challenge on manufacturing, thus optical proximity correction (OPC) is widely applied in conventional design flow for manufacturability optimization. Traditional techniques conduct OPC by leveraging a lithography model but may suffer from prohibitive computational overhead. In addition, most of them focus on optimizing a single and local clip instead of addressing how to tackle the full-chip scale. In this paper, we present DAMO, a high performance and scalable deep learning-enabled OPC system for full-chip scale. It is an end-to-end mask optimization paradigm that contains a deep lithography simulator (DLS) for lithography modeling and a deep mask generator (DMG) for mask pattern generation. Moreover, a novel layout splitting algorithm customized for DAMO is proposed to handle full-chip OPC problem. Extensive experiments show that DAMO outperforms state-of-the-art OPC solutions in both academia and industrial commercial toolkit.

 

 

 

 

 

AI+EDA

Lithography