https://circuitnet.github.io/ 

CircuitNet is an open-source dataset dedicated to machine learning (ML) applications in electronic design automation (EDA). They have collected more than 20K samples from versatile runs of commercial design tools based on open-source designs with various features for multiple ML for EDA applications.

 

 

 

https://github.com/OpenROAD-Assistant/EDA-Corpus

EDA Corpus is a data corpus for Electronic Design Automation (EDA) Large Language Model (LLM) research. In particular, the datapoints are tailored to OpenROAD and OpenROAD-flow-scripts. The corpus contains datasets for both question-answering and prompt-scripting for OpenROAD to improve user productivity.

 

 

 

https://github.com/drexel-ice/EDA-schema 

EDA-schema is a property graph data model schema developed to represent digital circuit designs and the associated attributes. The contributions of this work include: 1) A standardized set of graph structures and feature sets representing a digital circuit and corresponding subcomponents. 2) A dataset of physical designs generated from the IWLS'05 benchmark circuit suite utilizing the open-source 130 nm Process Design Kit (PDK) provided by Skywater and the open-source toolset OpenROAD.

 

 

 

https://slice-ml-eda.github.io/ 

The SLICE project aims to overcome the barriers to applying machine learning (ML) techniques to electronic design automation (EDA) and chip design problems by building a shareable and extensible infrastructure containing unified design environments, software interfaces between EDA tools and ML platforms, labeled datasets, and pre-trained ML models. Motivated by the spectacular success of the flywheel effect of infrastructure in the broader AI, SLICE aims to create a similar effect for the ML EDA flywheel by establishing an open infrastructure.

 

 

 

https://github.com/hkust-zhiyao/RTLLM

RTL Generation with Large Language Model Benchmark for generating design RTL with natural language (under construction). This repository contains a total of 29 designs. Each design has its own folder, which includes several files.

 

 

 

https://github.com/hkust-zhiyao/SpecLLM

SpecLLM: Exploring Generation and Review of VLSI Design Specification with Large Language Model. We propose a structured definition of architecture specifications, categorizing them into three distinct abstraction levels. Leveraging this definition, we create and release a specification dataset by methodically gathering 46 architecture specification documents from various public sources. Our clear definitions of architecture specifications, coupled with the dataset we have formed, lay a solid foundation for prospective research in employing LLMs for architecture specifications.

 

 

 

https://github.com/NVlabs/verilog-eval

This is an evaluation harness for the VerilogEval problem solving dataset described in the paper "VerilogEval: Evaluating Large Language Models for Verilog Code Generation". This evaluation dataset consists of 156 problems from the Verilog instructional website HDLBits. We provide two sets of problem descriptions: machine generated and manually converted to text-only format.

 

 

 

https://github.com/hkust-zhiyao/RTL-Coder 

Targeting Verilog code generation, we propose an automated flow to generate a large labeled dataset with over 27,000 diverse Verilog design problems and answers. It addresses the serious data availability challenge in IC design-related tasks, and its potential applications are not limited to LLMs. The LLM directly trained on it can already achieve comparable accuracy with GPT-3.5.

 

 

 

https://github.com/Yu-Utah/Gamora

Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks. We propose a novel symbolic reasoning framework exploiting graph neural networks (GNNs) and GPU acceleration to reason high-level functional blocks from gate-level netlists, namely Gamora, which offers high reasoning performance w.r.t exact reasoning algorithms, strong scalability to BNs with over 33 million nodes, and generalization capability from simple to complex designs.

 

 

 

https://yu-maryland.github.io/Verilog-to-PyG/

We introduce an innovative open-source framework that translates RTL designs into graph representation foundations, which can be seamlessly integrated with the PyTorch Geometric graph learning platform. Furthermore, the Verilog-to-PyG (V2PYG) framework is compatible with the open-source Electronic Design Automation (EDA) toolchain OpenROAD, facilitating the collection of labeled datasets in an utterly open-source manner. Additionally, we will present novel RTL data augmentation methods (incorporated in our framework) that enable functional equivalent design augmentation for the construction of an extensive graph-based RTL design database.

 

 

 

https://github.com/hkust-zhiyao/MasterRTL

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design. we propose an innovative pre-synthesis PPA estimation framework named MasterRTL. It first converts the HDL code to a new bit-level design representation named the simple operator graph (SOG). By only adopting single-bit simple operators, this SOG proves to be a general representation that unifies different design types and styles. The SOG is also more similar to the target gate-level netlist, reducing the gap between RTL representation and netlist. In addition to the new SOG representation, MasterRTL proposes new ML methods for the RTL-stage modeling of timing, power, and area separately.

 

 

 

https://github.com/cure-lab/DeepGate

Code repository for the paper: DeepGate: Learning Neural Representations of Logic Gates. DeepGate, a novel representation learning solution that effectively embeds both logic function and structural information of a circuit as vectors on each gate. Specifically, we propose transforming circuits into unified and-inverter graph format for learning and using signal probabilities as the supervision task in DeepGate. We then introduce a novel graph neural network that uses strong inductive biases in practical circuits as learning priors for signal probability prediction.

 

 

 

https://github.com/cure-lab/DeepGate2

DeepGate2: Functionality-Aware Circuit Representation Learning. We introduce DeepGate2, a novel functionality-aware learning framework that significantly improves upon the original DeepGate solution in terms of both learning effectiveness and efficiency. Our approach involves using pairwise truth table differences between sampled logic gates as training supervision, along with a well-designed and scalable loss function that explicitly considers circuit functionality. Additionally, we consider inherent circuit characteristics and design an efficient one-round graph neural network (GNN), resulting in an order of magnitude faster learning speed than the original DeepGate solution.

 

 

 

https://github.com/DfX-NYUAD/GNN-RE 

GNN-RE is a generic, graph neural network (GNN)-based platform for functional reverse engineering of circuits. GNN-RE 1) represents and analyzes flattened/ unstructured gate-level netlists, 2) automatically identifies the boundaries between the modules or sub-circuits implemented in such netlists, and 3) classifies the sub-circuits based on their functionalities.

 

 

 

https://github.com/UCLA-VAST/HARP 

This repo contains the codes for building HARP, an automated framework to be trained to act as the surrogate of the HLS tool. It can be used to expedite the design optimization process. The database used in this repo is built using the AMD/Xilinx HLS tools, but can be replaced by other databases. HARP develops a GNN-based model and builds a hierarchical graph to tackle the long range of dependency in programs. It also decouples the representation of program and its transformations (i.e., pragmas), allowing the model to learn the individual impact of each of these components. These optimizations not only enhance the performance of the model and the design space exploration based on it but also improve the model’s transfer learning capability, enabling easier adaptation to new environments.

 

 

 

https://github.com/shihuihong214/NASA-F 

This repository contains our PyTorch training code, evaluation code and pretrained models for NASA-F. NASA-F is an FPGA-oriented Neural Architecture Search (NAS) and Acceleration framework to search for and accelerate multiplication-reduced hybrid networks. This is the first FPGA-oriented algorithm and hardware co-design framework dedicated to hybrid DNN models.

 

 

 

https://github.com/Brilight/DeePEB 

DeePEB: A neural network based PEB solver to accelerate the PEB simulation without sacrificing accuracy. We construct DeePEB based on the observation of the physical essence of PEB: most of the dynamic information of the PEB process is contained in low-frequency modes of related reactants, and the high-frequency information affects the local features. So we combine both neural operator and customized convolution operations for learning the solution operator of PEB. Our algorithm is validated with an industry-strength software S-Litho under real manufacturing conditions, exhibiting high efficiency and accuracy.

 

 

 

https://github.com/phdyang007/dlhsd/tree/dct_as_conv 

This Repo Contains the Source Code and Pretrained Model for the Paper " Attacking a CNN-based Layout hotspot Detector Using Group Gradient Method". We examine the risk of state-of-the-art deep learning-based layout hotspot detectors under practical attack scenarios. We present an innovative adversarial attack formulation to attack the layout clips and propose a fast group gradient method to solve it.

 

 

 

https://github.com/phdyang007/dlhsd 

This Repo Contains the Source Code and Pretrained Model for the Paper " Layout Hotspot Detection with Feature Tensor Generation and Deep Biased Learning". We develop a deep learning framework for high performance and large scale hotspot detection. First, we use feature tensor generation to extract representative layout features that fit well with convolutional neural networks while keeping the spatial relationship of the original layout pattern with minimal information loss. Second, we propose a biased learning (BL) algorithm to train the convolutional neural network to further improve detection accuracy with small false alarm penalties.

 

 

 

https://github.com/google-research/circuit_training 

Circuit Training is an open-source framework for generating chip floor plans with distributed deep reinforcement learning. This framework reproduces the methodology published in the Nature 2021 paper. Our hope is that Circuit Training will foster further collaborations between academia and industry, and enable advances in deep reinforcement learning for Electronic Design Automation, as well as, general combinatorial and decision making optimization problems. Capable of optimizing chip blocks with hundreds of macros, Circuit Training automatically generates floor plans in hours, whereas baseline methods often require human experts in the loop and can take months. Circuit training is built on top of TF-Agents and TensorFlow 2.x with support for eager execution, distributed training across multiple GPUs, and distributed data collection scaling to 100s of actors.

 

 

 

https://github.com/syunlee/RL-Legalizer 

RL-Legalizer: Reinforcement Learning-based Mixed-Height Standard Cell Legalization, aims to resolve the suboptimality of existing sequential legalization algorithms with respect to displacement and wirelength. We propose a deep reinforcement learning framework to optimize cell priority in the legalization phase of various designs. We extract the selected features of movable cells and their surroundings, then embed them into cell-wise deep neural networks. We then determine cell priority and legalize them in order using a pixel-wise search algorithm. The proposed framework uses a policy gradient algorithm and several training techniques, including grid-cell subepisode, data normalization, reduced dimensional state, and network optimization.

 

 

 

https://github.com/Thinklab-SJTU/EDA-AI/tree/main 

DeepPlace: An end-to-end learning approach DeepPlace for placement problem with two stages. The deep reinforcement learning (DRL) agent places the macros sequentially, followed by a gradient-based optimization placer to arrange millions of standard cells. We use PPO for all the experiments implemented with Pytorch, and the GPU version of DREAMPlace is adopted as gradient based optimization placer for arranging standard cells. HubRouter: This is an implementation of the NeurIPS 2023 paper "HubRouter: Learning Global Routing via Hub Generation and Pin-hub Connection" (HubRouter). This approach is a global routing solver that includes a two-phase learning framework.

 

 

 

https://github.com/NVlabs/AutoDMP 

AutoDMP: Automated DREAMPlace-based Macro Placement. Built upon the GPU-accelerated global placer DREAMPlace and detailed placer ABCDPlace, AutoDMP adds simultaneous macro and standard cell placement enhancements and automatic parameter tuning based on multi-objective hyperparameter Bayesian optimization (MOBO).

 

 

 

https://github.com/limbo018/DREAMplace 

Deep learning toolkit-enabled VLSI placement. With the analogy between nonlinear VLSI placement and deep learning training problem, this tool is developed with deep learning toolkit for flexibility and efficiency. The tool runs on both CPU and GPU. Over 30X speedup over the CPU implementation (RePlAce) is achieved in global placement and legalization on ISPD 2005 contest benchmarks with a Nvidia Tesla V100 GPU. DREAMPlace also integrates a GPU-accelerated detailed placer, ABCDPlace, which can achieve around 16X speedup on million-size benchmarks over the widely-adopted sequential placer NTUPlace3 on CPU.

 

 

 

https://github.com/leorezende93/acc_dse_env 

A fast and accurate DSE approach for CNNs using an analytical model fitted from the physical synthesis of hardware accelerators. The model is integrated with CNN frameworks, like TensorFlow, to generate accurate results. The analytic model estimates area, performance, power, energy, and memory accesses.

 

 

 

https://github.com/TimingPredict/TimingPredict 

This is the official open source repository for "A Timing Engine Inspired Graph Neural Network Model for Pre-Routing Slack Prediction" (DAC 2022). we present a timing engine inspired graph neural network (GNN) to predict arrival time and slack at timing endpoints. We further leverage edge delays as local auxiliary tasks to facilitate model training with increased model performance.

 

 

 

https://github.com/zqj2333/PANDA 

Power efficiency is a critical design objective in modern microprocessor design. To evaluate the impact of architectural-level design decisions, an accurate yet efficient architecture-level power model is desired. However, widely adopted data-independent analytical power models like McPAT and Wattch have been criticized for their unreliable accuracy. While some machine learning (ML) methods have been proposed for architecture-level power modeling, they rely on sufficient known designs for training and perform poorly when the number of available designs is limited, which is typically the case in realistic scenarios. PANDA is an architecture-level power evaluation method by unifying analytical and machine learning solutions. We propose PANDA, an innovative architecture-level solution that combines the advantages of analytical and ML power models. It achieves unprecedented high accuracy on unknown new designs even when there are very limited designs for training, which is a common challenge in practice.

 

 

 

https://github.com/OSCC-Project/iEDA 

An open-source EDA infrastructure and tools from netlist to GDS for ASIC design, aim for building a basic infrastructure for EDA technology evolution and providing high quality and performance EDA tool. iEDA now covers the whole flow of physical design (including Floorplan, Placement, CTS, Routing, Timing Optimization etc.), and part of the analysis tools (Static Timing Analysis and Power Analysis). The main contents and plans include 1) Enhance the infrastructure to support more design requirement. 2) Complete the EDA tool chain from RTL-GDS II. 3) Improve the quality and performance of all EDA tool operations. 4) Construct AI for EDA platform and introduce trained AI mode to the EDA platform. 5) Build data system with enough chip design and labeling process data. 6) Achieve the adaptability of the EDA platform for cloud-native.

 

 

 

https://gitee.com/opendacs 

Opendacs is a national non-profit organization focused on open-source Electronic Design Automation (EDA) research. Its mission is to establish a global open-source initiative for circuit and system design automation tools, facilitating efficient communication and collaboration among chip and software/hardware design and development engineers worldwide. By doing so, Opendacs aims to expand their technical horizons and accelerate the iteration process in chip design, development, production, and commercialization. The organization's key areas of focus include chip design verification and test synthesis, logic synthesis and high-level synthesis, physical design and modeling verification, device modeling and parameter extraction, process models and Process Design Kits (PDK), printed circuit board (PCB) design and verification, as well as post-Moore, AI for EDA, and cloud platforms.

 

 

 

https://github.com/The-OpenROAD-Project/OpenROAD 

OpenROAD is the leading open-source, foundational application for semiconductor digital design. The OpenROAD flow delivers an Autonomous, No-Human-In-Loop (NHIL) flow, 24 hour turnaround from RTL-GDSII for rapid design exploration and physical design implementation. The mission of OpenROAD is that eliminates the barriers of cost, schedule risk and uncertainty in hardware design to promote open access to rapid, low-cost IC design software and expertise and system innovation.

 

 

 

AI+EDA

开源代码