2024 DAC

MAUnet: Multiscale Attention U-Net for Effective IR Drop Prediction

Author: Mingyue Wang, Yuanqing Cheng, Yage Lin, Kelin Peng, Shunchuan Yang, Zhou Jin, Wei W. Xing

Affiliation: Beihang University; Super Scientific Software Laboratory, China University of Petroleum-Beijing; The University of Sheffield

Abstract:

The efficient analysis of power grids is a crucial yet computationally challenging task in integrated circuit (IC) design, given the shrinking power supply voltage of ultra deep-submicron VLSI design. Different from conventional modified nodal analysis analytical solving technique, this paper introduces MAUnet, an innovative machine-learning mode that redefines state-ofthe-art full-chip static IR drop prediction. MAUnet ingeniously integrates multi-scale convolutional blocks, attention mechanisms, and U-Net architecture to optimize prediction accuracy. The multi-scale convolutional blocks significantly enhance feature extraction from image-based data, while the attention mechanism precisely identifies hotspot regions. The UNet architecture, on the other hand, enables scalable image-to-image prediction applicable to circuits of any size. Uniquely, MAUnet also incorporates a pioneering fusion method that synergies both power grids and image-based data. Additionally, we introduce a low-rank approximation transfer learning technique to extend MAUnet's applicability to unseen test cases. Benchmark tests validate MAUnet's superior performance, achieving an average error of less than 6% relative to the average IR drop on three benchmarks.The performance enhancements offered by our proposed method are substantial, outperforming the current state-of-the-art method, IREDGe, by considerable margins of 29%, 65%, and 68% in three canonical benchmarks. Transfer learning is validated to enable mode to achieve effective improvement on real circuit test cases. Compared to commercial tools, which often require hours to deliver results, the proposed method provides orders of magnitude speed-up with negligible error in practice.

 

 

 

 

2024 TCAS-II

A 3-D Convolutional Network for Fast and Accurate S/Z-Parameters Prediction of Si-Interposer Power Distribution Network With Through Silicon Vias

Author: Deguang Yang, Gang Dong, Changle Zhi, Daihang Liu, Yinghao Feng, Yintang Yang

Affiliation: School of Microelectronics, Xidian University, Xi’an, China

Abstract:

In this brief, based on a 3D coarse mode extraction method and the 3D convolutional neural network (3D CNN), a full-3D Artificial Intelligence(AI) method, namely C3D-CNN (Coarse 3D Convolutional Neural Network) is proposed to estimate the S-parameters and Z-parameters of interposer PDNs efficiently and accurately with TSVs considered. Three interposer PDN modes with different metal densities and pitches are built to train and verify our method. Results of our mode are compared with those obtained by a conventional finite element method (FEM) simulator (HFSS), a regular AI method (Fully Connected Neural Network, FCNN) and a conventional Machine Learning (ML) method (Gradient Boosting Decision Tree, GBDT). The calculation time of S-parameters and -parameters of a 4-port PDN mode for 300 frequency points reduces from 600 seconds (HFSS) to 0.1 seconds by using our C3D-CNN method. Also, the accuracy of the proposed C3D-CNN method is 53.51% and 11.68% higher than that of FCNN and GBDT, respectively. The results show that our AI method can significantly reduce the calculation time and improve the accuracy of PDN analysis.

 

 

 

 

2023 DAC

Late Breaking Results: RL-LPO: Reinforcement Learning Based Leakage Power Optimization Framework with Graph Neural Network

Author: Peng Cao, Jiahao Wang

Affiliation: National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China

Abstract:

Leakage power optimization based on threshold voltage (Vth) assignment poses great challenge in circuit design due to its tremendous solution space. In this paper, a Reinforcement Learning-based Leakage Power Optimization framework (RL-LPO) is first-ever proposed to formulate Vth assignment as a reinforcement learning (RL) process by learning timing and physical characteristics of each circuit instance with Graph Neural Networks (GNN). The proposed RL-LPO was validated by the IWLS2005 and Opencores benchmark circuits with TSMC 28nm technology and experimental results demonstrate that our work achieves better leakage power optimization by additional 3% reduction on average than the commercial tool PrimeTime with 6.7× speed up when being transferred to unseen circuits with negligible timing degradation.

 

 

 

 

2023 ICCAD

Power Distribution Network Optimization Using HLA-GCN for routability Enhancement

Author: Younggwang Jung, Daijoon Hyun, Soyoon Choi, Youngsoo Shin

Affiliation: School of Electrical Engineering, KAIST, Daejeon, Korea; Department of Semiconductor Systems Engineering, Sejong University, Seoul, Korea

Abstract:

Power distribution network (PDN) consumes many routing resources to satisfy IR-drop constraints. With the increasing IR drop and the decreasing metal tracks in recent technology, the design of PDN becomes very important for circuit routing. In this paper, post-placement PDN optimization is proposed for routability enhancement. For a given regular PDN, we iteratively remove partial straps that have a small impact on IR-drop while improving routing overflow. Hierarchical layout-aware graph convolutional network (HLA-GCN) is introduced to find the candidate areas for strap removal, and one area is selected based on scoring. This process is applied twice to reduce the candidates for strap removal, and one strap is finally chosen after identifying the actual impact on IR-drop and routing congestion. This method is enabled by fast incremental IR-drop analysis using PDN-GCN, which classifies nodes with voltage change to update only those nodes in the modified nodal analysis. Experimental results address that the proposed method reduces routing overflow by 16% in an acceptable time, where IR-drop values are updated quickly with high accuracy of less than 2% error.

 

 

 

 

2023 ICCAD

Invited Paper: 2023 ICCAD CAD Contest Problem C: Static IR Drop Estimation Using Machine Learning

Author: Gana Surya Prakash Kadagala, Vidya A. Chhabria

Affiliation: Arizona State University

Abstract:

Power delivery network (PDN) analysis is a critical aspect of the design cycle to ensure the power grid meets the current demands of the chip. Static IR drop simulation, performed as a part of PDN analysis, is crucial to the estimation of the worstcase voltage drop (IR) drop of the chip which in turn determines chip frequency and functionality. Algorithmically, the static IR drop simulation amounts to solving a large system of linear equations with billions of variables and is computationally very expensive with significantly large runtimes. This contest aims at leveraging machine learning (ML) techniques to overcome this challenge. While previous research has introduced ML-based solutions for static IR drop simulation, their performance remains untested on standardized benchmarks, obscuring the true state-of-the-art ML mode. The contest releases twenty real circuit (split as ten seen during training and ten as hidden) benchmarks and hundreds of synthetic benchmarks for training ML modes to predict IR drop. The synthetic data serves as a training dataset, which can then be fine-tuned using limited real circuit data for accurate predictions on unseen testcases. The goal of the contest is to train novel ML algorithms to perform the prediction with high accuracy, F1 score, and low runtimes.

 

 

 

 

2023 ASP-DAC

Learning Based Spatial Power Characterization and Full-Chip Power Estimation for Commercial TPUs

Author:Jincong Lu, Jinwei Zhang, Wentian Jin, Sachin Sachdeva, Sheldon X.-D. Tan

Affiliation: Department of Electrical and Computer Engineering;University of California, Riverside;Riverside, California, United States

Abstract:

In this paper, we propose a novel approach for the real-time estimation of chip-level spatial power maps for commercial Google Coral M.2 TPU chips based on a machine-learning technique for the first time. The new method can enable the development of more robust runtime power and thermal control schemes to take advantage of spatial power information such as hot spots that are otherwise not available. Different from the existing commercial multi-core processors in which real-time performance-related utilization information is available, the TPU from Google does not have such information. To mitigate this problem, we propose to use features that are related to the workloads of running different deep neural networks (DNN) such as the hyperparameters of DNN and TPU resource information generated by the TPU compiler. The new approach involves the offline acquisition of accurate spatial and temporal temperature maps captured from an external infrared thermal imaging camera under nominal working conditions of a chip. To build the dynamic power density map mode, we apply generative adversarial networks (GAN) based on the workload-related features. Our study shows that the estimated total powers match the manufacturer's total power measurements extremely well. Experimental results further show that the predictions of power maps are quite accurate, with the RMSE of only 4.98mW/mm 2 , or 2.6% of the full-scale error. The speed of deploying the proposed approach on an Intel Core i7-10710U is as fast as 6.9ms, which is suitable for real-time estimation.

 

 

 

 

2022 DAC

Worst-case Dynamic Power Distribution Network Noise Prediction Using Convolutional Neural Network

Author: Xiao Dong, Yufei Chen, Xunzhao Yin, Cheng Zhuo

Affiliation: College of Information Science & Electronic Engineering, Zhejiang University, Hangzhou, China

Abstract:

Worst-case dynamic PDN noise analysis is an essential step in PDN sign-off to ensure the performance and reliability of chips. However, with the growing PDN size and increasing scenarios to be validated, it becomes very time- and resource-consuming to conduct full-stack PDN simulation to check the worst-case noise for different test vectors. Recently, various works have proposed machine learning based methods for supply noise prediction, many of which still suffer from large training overhead, inefficiency, or non-scalability. Thus, this paper proposed an efficient and scalable framework for the worst-case dynamic PDN noise prediction. The framework first reduces the spatial and temporal redundancy in the PDN and input current vector, and then employs efficient feature extraction as well as a novel convolutional neural network architecture to predict the worst-case dynamic PDN noise. Experimental results show that the proposed framework consistently outperforms the commercial tool and the state-of-the-art machine learning method with only 0.63--1.02% mean relative error and 25--69× speedup.

 

 

 

 

2022 ASP-DAC

Vector-based Dynamic IR-drop Prediction Using Machine Learning

Author: Jia-Xian Chen, Shi-Tang Liu, Yu-Tsung Wu, Mu-Ting Wu, Chien-Mo James Li, Norman Chang, Ying-Shiun Li, Wentze Chuang

Affiliation: Graduate Institute of Electronics Engineering,National Taiwan University, Taiwan;Ansys Inc.

Abstract:

Vector-based dynamic IR-drop analysis of the entire vector set is infeasible due to long runtime. In this paper, we use machine learning to perform vector-based IR drop prediction for all logic cells in the circuit. We extract important features, such as toggle counts and arrival time, directly from the logic simulation waveform so that we can perform vector-based IR-drop prediction quickly. We also propose a feature engineering method, density map, to increase correlation by 0.1. Our method is scalable because the feature dimension is fixed (72), independent of design size and cell library. Our experiments show that the mean absolute error of the predictor is less than 3% of the nominal supply voltage. We achieve more than 495 speedups compared to a popular commercial tool. Our machine learning prediction can be used to identify IR-drop risky vectors from the entire test vector set, which is infeasible using traditional IR-drop analysis.

 

 

 

 

2022 ASP-DAC

A Graph Neural Network Method for Fast ECO Leakage Power Optimization

Author: Kai Wang, Peng Cao

Affiliation: National ASIC System Engineering Technology Research Center, Southeast University, Nanjing, China

Abstract:

In modern design, engineering change order (ECO) is often utilized to perform power optimization including gate-sizing and Vth-assignments, which is efficient but highly timing consuming. Many graph neural network (GNN) based methods are recently proposed for fast and accurate ECO power optimization by considering neighbors' information. Nonetheless, these works fail to learn high-quality node representations on directed graph since they treat all neighbors uniformly when gathering their information and lack local topology information from neighbors one or two-hop away. In this paper, we introduce a directed GNN based method which learns information from different neighbors respectively and contains rich local topology information, which was validated by the Opencores and IWLS 2005 benchmarks with TSMC 28nm technology. Experimental results show that our approach outperforms prior GNN based methods with at least 7.8% and 7.6% prediction accuracy improvement for seen and unseen designs respectively as well as 8.3% to 29.0% leakage optimization improvement. Compared with commercial EDA tool Primetime, the proposed framework achieves similar power optimization results with up to 12X runtime improvement.

 

 

 

 

2021 ICCAD

BeGAN: Power Grid Benchmark Generation Using a Process-portable GAN-based Methodology

Author: Vidya A. Chhabria, Kishor Kunal, Masoud Zabihi, Sachin S. Sapatnekar

Affiliation: University of Minnesota, Minneapolis, MN

Abstract:

Evaluating CAD solutions to physical implementation problems has been extremely challenging due to the unavailability of modern benchmarks in the public domain. This work aims to address this challenge by proposing a process-portable machine learning (ML)-based methodology for synthesizing synthetic power delivery network (PDN) benchmarks that obfuscate intellectual property information. In particular, the proposed approach leverages generative adversarial networks (GAN) and transfer learning techniques to create realistic PDN benchmarks from a small set of available real circuit data. BeGAN generates thousands of PDN benchmarks with significant histogram correlation (p-value ≤ 0.05) demonstrating its realism and an average L1 Norm of more than 7.1 %, highlighting its IP obfuscation capabilities. The original and thousands of ML-generated synthetic PDN benchmarks for four different open-source technologies are released in the public domain to advance research in this field.

 

 

 

 

2020 ASP-DAC

PowerNet Transferable Dynamic IR Drop Estimation via Maximum Convolutional Neural Network

Author: Zhiyao Xie, Haoxing Ren, Brucek Khailany, Ye Sheng, Santosh Santosh, Jiang Hu, Yiran Chen

Affiliation: Duke University, Nvidia Corporation, Texas A&M University

Abstract:

IR drop is a fundamental constraint required by almost all chip designs. However, its evaluation usually takes a long time that hinders mitigation techniques for fixing its violations. In this work, we develop a fast dynamic IR drop estimation technique, named PowerNet, based on a convolutional neural network (CNN). It can handle both vector-based and vectorless IR analyses. Moreover, the proposed CNN mode is general and transferable to different designs. This is in contrast to most existing machine learning (ML) approaches, where a mode is applicable only to a specific design. Experimental results show that PowerNet outperforms the latest ML method by 9% in accuracy for the challenging case of vectorless IR drop and achieves a 30× speedup compared to an accurate IR drop commercial tool. Further, a mitigation tool guided by PowerNet reduces IR drop hotspots by 26% and 31% on two industrial designs, respectively, with very limited modification on their power grids.

 

 

 

 

2020 DATE

XGBIR: An XGBoost-based IR drop predictor for power delivery network

Author: Chi-Hsien Pao, An-Yu Su, and Yu-Min Lee

Affiliation: Institute of Communications Engineering, College of Electrical and Computer Engineering

Abstract:

This work utilizes the XGBoost to build a machine-learning-based IR drop predictor, XGBIR, for the power grid. To capture the behavior of power grid, we extract its several features and employ its locality property to save the extraction time. XGBIR can be effectively applied to large designs and the average error of predicted IR drops is less than 6 mV.

 

 

 

 

2020 ICCAD

GridNet Fast Data-Driven EM-Induced IR Drop Prediction and Localized Fixing for On-Chip Power Grid Networks

Author: Han Zhou, Wentian Jin, and Sheldon X.-D. Tan

Affiliation: Department of Electrical and Computer Engineering, University of California, Riverside, CA 92521

Abstract:

Electromigration (EM) is a major failure effect for on-chip power grid networks of deep submicron VLSI circuits. EM degradation of metal grid lines can lead to excessive voltage drops (IR drops) before the target lifetime. In this paper, we propose a fast data-driven EM-induced IR drop analysis framework for power grid networks, named GridNet, based on the conditional generative adversarial networks (CGAN). It aims to accelerate the incremental full-chip EM-induced IR drop analysis, as well as IR drop violation fixing during the power grid design and optimization. More importantly, GridNet can naturally leverage the differentiable feature of deep neural networks (DNN) to obtain the sensitivity information of node voltage with respect to the wire resistance (or width) with marginal cost. Grid-Net treats continuous time and the given electrical features as input conditions, and the EM-induced time-varying voltage of power grid networks as the conditional outputs, which are represented as data series images. We show that GridNet is able to learn the temporal dynamics of the aging process in continuous time domain. Besides, we can take advantage of the sensitivity information provided by GridNet to perform efficient localized IR drop violation fixing in the late stage design and optimization. Numerical results on 36000 synthesized power grid network samples demonstrate that the new method can lead to 10 5 × speedup over the recently proposed full-chip coupled EM and IR drop analysis tool. We further show that localized IR drop violation fix for the same set of power grid networks can be performed remarkably efficiently using the cheap sensitivity computation from GridNet.

 

 

 

 

2020 ASP-DAC

Template-based PDN Synthesis in Floorplan and placement Using Classifier and CNN Techniques

Author: Vidya A. Chhabria, Andrew B. Kahng, Minsoo Kim, Uday Mallappa, Sachin S. Sapatnekar, and Bangqi Xu

Affiliation: University of Minnesota;University of California, San Diego

Abstract:

Designing an optimal power delivery network (PDN) is a time-intensive task that involves many iterations. This paper proposes a methodology that employs a library of predesigned, stitchable templates, and uses machine learning (ML) to rapidly build a PDN with region-wise uniform pitches based on these templates. Our methodology is applicable at both the floorplan and placement stages of physical implementation. (i) At the floorplan stage, we synthesize an optimized PDN based on early estimates of current and congestion, using a simple multilayer perceptron classifier. (ii) At the placement stage, we incrementally optimize an existing PDN based on more detailed congestion and current distributions, using a convolution neural network. At each stage, the neural network builds a safe-by-construction PDN that meets IR drop and electromigration (EM) specifications. On average, the optimization of the PDN brings an extra 3% of routing resources, which corresponds to a thousands of routing tracks in congestion-critical regions, when compared to a globally uniform PDN, while staying within the IR drop and EM limits.

 

 

 

 

2019 ASP-DAC

Learning-based Prediction of Package Power Delivery Network Quality

Author: Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas and Bangqi Xu

Affiliation: CSE and ECE Departments, UC San Diego, La Jolla, CA, USA

Abstract:

Power Delivery Network (PDN) is a critical component in modern System-on-Chip (SoC) designs. With the rapid development in applications, the quality of PDN, especially Package (PKG) PDN, de-termines whether a sufficient amount of power can be delivered to critical computing blocks. In conventional PKG design, PDN design typically takes multiple weeks including many manual iterations for optimization. Also, there is a large discrepancy between (i) quick simulation tools used for quick PDN quality assessment during the design phase, and (ii) the golden extraction tool used for signoff. This discrepancy may introduce more iterations. In this work, we propose a learning-based methodology to perform PKG PDN quality assessment both before layout (when only bump/ball maps, but no package routing, are available) and after layout (when routing is completed but no signoff analysis has been launched). Our contributions include (i) identification of important parameters to estimate the achievable PKG PDN quality in terms of bump inductance; (ii) the avoidance of unnecessary manual trial and error overheads in PKG PDN design; and (iii) more accurate design-phase PKG PDN quality assessment. We validate accuracy of our predictive modes on PKG designs from industry. Experimental results show that, across a testbed of 17 industry PKG designs, we can predict bump inductance with an average absolute percentage error of 21.2% or less, given only pinmap and technology information. We improve prediction accuracy to achieve an average absolute percentage error of 17.5% or less when layout information is considered.

 

 

 

 

2019 ICCAD

IncPIRD: Fast Learning-based Prediction of Incremental IR Drop

Author: Chia-Tung Ho and Andrew B Kahng

Affiliation: CSE and 2ECE Departments, UC San Diego, La Jolla, CA, USA

Abstract:

The on-chip power delivery network (PDN) is an essential element of physical implementation that strongly determines functionality, quality and reliability of a given IC product. To meet IR drop requirements, a denser power grid is desirable. On the other hand, to meet timing and layout density requirements, a sparser power grid leaves more resources for routing. Often, numerous time-consuming iterations among PDN design, IR analysis, and floorplanning or placement are needed during the physical implementation of modern high-performance designs. Thus, fast and accurate incremental IR prediction has emerged as a critical need, as it can potentially reduce the turnaround time between design and analysis and help improve design convergence. In this work, we apply superposition and partitioning techniques to extract relevant electrical features of a given SOC floorplan and PDN. We then use a machine learning mode to predict the updated static IR drop for each power node (having tap current source attached) in the design throughout a series of changes (PDN modification, block movement, block power change, power pad movement) to the SOC floorplan, without needing to rerun a golden IR drop tool. We develop our mode with more than 150 generated SOC floorplans with different PDN structures in 28nm foundry technology. Compared to an industry-leading, golden IR drop signoff tool (ANSYS RedHawk), we achieve 20-1000× speedup with less than 1 mV average absolute error and approximately 5m V maximum absolute error.

 

 

 

 

2019 ASP-DAC

Learning-based Prediction of Package Power Delivery Network Quality

Author: Yi Cao, Andrew B. Kahng, Joseph Li, Abinash Roy, Vaishnav Srinivas, and Bangqi Xu

Affiliation: CSE and ECE Departments, UC San Diego, La Jolla, CA, USA; Qualcomm Technologies, Inc., San Diego, CA, USA

Abstract:

Power Delivery Network (PDN) is a critical component in modern System-on-Chip (SoC) designs. With the rapid development in applications, the quality of PDN, especially Package (PKG) PDN, de-termines whether a sufficient amount of power can be delivered to critical computing blocks. In conventional PKG design, PDN design typically takes multiple weeks including many manual iterations for optimization. Also, there is a large discrepancy between (i) quick simulation tools used for quick PDN quality assessment during the design phase, and (ii) the golden extraction tool used for signoff. This discrepancy may introduce more iterations. In this work, we propose a learning-based methodology to perform PKG PDN quality assessment both before layout (when only bump/ball maps, but no package routing, are available) and after layout (when routing is completed but no signoff analysis has been launched). Our contributions include (i) identification of important parameters to estimate the achievable PKG PDN quality in terms of bump inductance; (ii) the avoidance of unnecessary manual trial and error overheads in PKG PDN design; and (iii) more accurate design-phase PKG PDN quality assessment. We validate accuracy of our predictive models on PKG designs from industry. Experimental results show that, across a testbed of 17 industry PKG designs, we can predict bump inductance with an average absolute percentage error of 21.2% or less, given only pinmap and technology information. We improve prediction accuracy to achieve an average absolute percentage error of 17.5% or less when layout information is considered.

 

 

 

 

2019 ICCAD

IncPIRD Fast Learning-Based Prediction of Incremental IR Drop

Author: Chia-Tung Ho,Andrew B. Kahng

Affiliation: CSE and 2ECE Departments, UC San Diego, La Jolla, CA, USA

Abstract:

The on-chip power delivery network (PDN) is an essential element of physical implementation that strongly determines functionality, quality and reliability of a given IC product. To meet IR drop requirements, a denser power grid is desirable. On the other hand, to meet timing and layout density requirements, a sparser power grid leaves more resources for routing. Often, numerous time-consuming iterations among PDN design, IR analysis, and floorplanning or placement are needed during the physical implementation of modern high-performance designs. Thus, fast and accurate incremental IR prediction has emerged as a critical need, as it can potentially reduce the turnaround time between design and analysis and help improve design convergence. In this work, we apply superposition and partitioning techniques to extract relevant electrical features of a given SOC floorplan and PDN. We then use a machine learning model to predict the updated static IR drop for each power node (having tap current source attached) in the design throughout a series of changes (PDN modification, block movement, block power change, power pad movement) to the SOC floorplan, without needing to rerun a golden IR drop tool. We develop our model with more than 150 generated SOC floorplans with different PDN structures in 28nm foundry technology. Compared to an industry-leading, golden IR drop signoff tool (ANSYS RedHawk), we achieve 20-1000× speedup with less than 1 mV average absolute error and approximately 5m V maximum absolute error.

 

 

 

 

2018 ICCAD

Machine-learning-based dynamic IR drop prediction for ECO

Author: Yen-Chun Fang, Heng-Yi Lin, Min-Yan Sui, Chien-Mo Li, and Eric Jia-Wei Fang

Affiliation: Graduate Institute of Electronics Engineering

Abstract:

During design signoff, many iterations of Engineer Change Order (ECO) are needed to ensure IR drop of each cell instance meets the specified limit. It is a waste of resources because repeated dynamic IR drop simulations take a very long time on very similar designs. In this work, we train a machine learning mode, based on data before ECO, and predict IR drop after ECO. To increase our prediction accuracy, we propose 17 timing-aware, power-aware, and physical-aware features. Our method is scalable because the feature dimension is fixed (937), independent of design size and cell library. Also, we propose to build regional modes for cell instances near IR drop violations to improves both prediction accuracy and training time. Our experiments show that our prediction correlation coefficient is 0.97 and average error is 3.0mV on a 5-million-cell industry design. Our IR drop prediction for 100K cell instances can be completed within 2 minutes. Our proposed method provides a fast IR drop prediction to speedup ECO.

 

 

 

 

AI+EDA

Power delivery network prediction