2023 TCAD

PROS 2.0: A Plug-In for routability Optimization and routed Wirelength Estimation Using Deep Learning

Author: Jingsong Chen, Jian Kuang, Guowei Zhao, Dennis J.-H. Huang, Evangeline F. Y. Young

Affiliation: Digital & Signoff Group, Cadence Design Systems, San Jose, CA, USA; Department of Computer Science and Engineering, The Chinese University of Hong Kong, Hong Kong

Abstract:

Recently, the topic of how to utilize prior knowledge obtained by machine-learning (ML) techniques during the EDA flow has been widely studied. In this article, we study this topic and propose a practical plug-in named PROS for both routability optimization and routed wirelength estimation which can be applied in the state-of-the-art commercial EDA tool or an academic EDA flow with negligible runtime overhead. PROS consists of three parts: 1) an effective fully convolutional network (FCN)-based predictor that only utilizes the data from placement result to forecast global routing (GR) congestion; 2) a parameter optimizer that can reasonably adjust GR cost parameters based on the prediction result to generate a better GR solution for detailed routing (DR); and 3) a convolutional neural network (CNN)-based wirelength estimator which can report accurate routed wirelength at the placement stage by using the predicted GR congestion. Experiments show that on the industrial benchmark suite in the advanced technology node, PROS can achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations by 11.65% on average, and on the DAC-2012 benchmark suite, PROS can achieve a very low error rate (1.82%) for wirelength estimation which greatly outperforms that of FLUTE (21.52%) by 19.70%.

 

 

 

 

2023 ICCAD

Invited Paper: Accelerating routability and timing Optimization with Open-Source AI4EDA Dataset CircuitNet and Heterogeneous Platforms

Author: Xun Jiang, Zizheng Guo, Zhuomin Chai, Yuxiang Zhao, Yibo Lin, Runsheng Wang, Ru Huang

Affiliation: School of Integrated Circuits, Peking University, Beijing, China

Abstract:

Routability and timing are two critical metrics for modern VLSI circuits. With increasing design complexity and continuous shrinking of technology nodes, optimizing routability and timing become extremely expensive due to high computational overhead for analysis. It is reported that conventional CPU-based parallelization strategies can no longer scale beyond 8–16 threads. In this talk, we introduce how to accelerate routability and timing optimization leveraging AI-enabled GPU acceleration. To break the inter-stage information dependency in conventional physical design flow, we build AI for EDA modes with an open-source dataset, CircuitNet, to enable ultrafast design optimization on GPU. We hope our study can shed lights to future development of EDA tools with AI-enabled heterogenity.

 

 

 

 

2023 ICCAD

Routability Prediction and Optimization Using Explainable AI

Author: Seonghyeon Park, Daeyeon Kim, Seongbin Kwon, Seokhyeong Kang

Affiliation: Department of Electrical Engineering, POSTECH, Republic of Korea

Abstract:

Machine learning (ML) techniques have been widely studied to predict routability in early-stage. To reduce the design turn-around time during the placement and routing iterations, it is crucial to predict the design rule violation (DRV) hotspots precisely before actual detailed routing. However, complex network architectures of ML make it challenging for humans to understand how ML generates predictions and to identify the factors that significantly influence the predictions. This black-box nature of ML limits the efficient integration of the prediction techniques into an optimization process. Explainable artificial intelligence enables the interpretation of decision rationales in the ML mode and brings us the reasons underlying the prediction of the mode. In this paper, we propose a routability optimization framework that analyzes the input features relevant to the predicted DRV hotspots using an explainable mode and selects the most suitable optimization methods. The proposed framework comprises three steps - (1) predicting DRV hotspots in the early-global routing stage, (2) calculating how much each input feature contributes to the predictions and (3) applying a proper optimization method to improve the routability. We reduced the number of DRVs by 78% on average in 16 design layouts without degrading the design Quality.

 

 

 

 

2023 ICCD

ClusterNet: routing Congestion Prediction and Optimization Using Netlist Clustering and Graph Neural Networks

Author: Kyungjun Min, Seongbin Kwon, Sung-Yun Lee, Dohun Kim, Sunghye Park, Seokhyeong Kang

Affiliation: Department of Electrical Engineering, Pohang;University of Science and Technology, Pohang, Republic of Korea

Abstract:

Accurately predicting routing congestion caused by netlist topology is essential as circuit designs become increasingly complex. To correctly predict routing congestion, the use of graph neural networks (GNNs) has gained great attention. However, existing GNN-based methods have limitations in capturing crucial netlist information and effectively representing complex topologies. In this work, we propose a novel approach, ClusterNet, to predict routing congestion caused by netlist topology. Our approach leverages netlist clustering to overcome these limitations. We first divide the netlist into highly connected clusters using the Leiden algorithm, enabling an analysis of the local netlist topology. We then predict routing congestion by exploiting GNNs to generate cluster embeddings that capture the detailed netlist topology. In addition, we introduce a cluster padding method that utilizes the trained mode to mitigate routing congestion. By applying the proposed ClusterNet, we can accurately predict and optimize routing congestion from specific cluster topologies. Our experimental results demonstrated improved prediction performance, with a mean absolute error of 0.056 and an R2 score of 0.669. Furthermore, routing congestion optimization significantly improved the total negative slack and reduced the number of failing endpoints by 14.5% and 9.9%, respectively.

 

 

 

 

2023 DATE

Routability Prediction using Deep Hierarchical Classification and Regression

Author: Daeyeon Kim, Jakang Lee, Seokhyeong Kang

Affiliation: EE Department, POSTECH, Pohang, South Korea

Abstract:

Routability prediction can forecast the locations where design rule violations occur without routing and thus can speed up the design iterations by skipping the time-consuming routing tasks. This paper investigated (i) how to predict the routability on a continuous value and (ii) how to improve the prediction accuracy for the minority samples. We propose a deep hierarchical classification and regression (HCR) mode that can detect hotspots with the number of violations. The hierarchical inference flow can prevent the mode from overfitting to the majority samples in imbalanced data. In addition, we introduce a training method for the proposed HCR mode that uses Bayesian optimization to find the ideal modeing parameters quickly and incorporates transfer learning for the regression mode. We achieved an R2 score of 0.71 for the regression and increased the Fl score in the binary classification by 94% compared to previous work.

 

 

 

 

2022 ASP-DAC

High-Correlation 3D routability Estimation for Congestion-guided Global routing

Author: Miaodi Su, Hongzhi Ding, Shaohong Weng, Changzhong Zou, Zhonghua Zhou, Yilu Chen, Jianli Chen, Yao-Wen Chang

Affiliation: College of Mathematics and Computer Science, Fuzhou University, Fuzhou 350108, China;Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, Canada;State Key Lab of ASIC & System, Fudan University, Shanghai 200433, China;Graduate Institute of Electronics Engineering, National Taiwan University, Taipei 10617, Taiwan;Department of Electrical Engineering, National Taiwan University, Taipei 10617, Taiwan

Abstract:

Routability estimation identifies potentially congested areas in advance to achieve high-quality routing solutions. To improve the routing quality, this paper presents a deep learning-based congestion estimation algorithm that applies the estimation to a global router. Unlike existing methods based on traditional compressed 2D features for model training and prediction, our algorithm extracts appropriate 3D features from the placed netlists. Furthermore, an improved RUDY (Rectangular Uniform wire DensitY) method is developed to estimate 3D routing demands. Besides, we develop a congestion estimator by employing a U-net model to generate a congestion heatmap, which is predicted before global routing and serves to guide the initial pattern routing of a global router to reduce unexpected overflows. Experimental results show that the Pearson Correlation Coefficient (PCC) between actual and our predicted congestion is high at about 0.848 on average, significantly higher than the counterpart by 21.14%. The results also show that our guided routing can reduce the respective routing overflows, wirelength, and via count by averagely 6.05%, 0.02%, and 1.18%, with only 24% runtime overheads, compared with the state-of-the-art CUGR global router that can balance routing quality and efficiency very well. In particular, our work provides a new generic machine learning model for not only routing congestion estimation demonstrated in this paper, but also general layout optimization problems.

 

 

 

 

2022 DAC

LHNN: Lattice Hypergraph Neural Network for VLSI Congestion Prediction

Author: Bowen Wang, Guibao Shen, Dong Li, Jianye Hao, Wulong Liu, Yu Huang, Hongzhong Wu, Yibo Lin, Guangyong Chen, Pheng-Ann Heng

Affiliation: Department of Computer Science and Engineering, The Chinese University of Hong Kong; Guangdong Provincial Key Laboratory of Computer Vision and Virtual Reality Technology, Shenzhen Institutes of Advanced Technology, Chinese Academy of Sciences; Huawei Noah’s Ark Lab; Department of Computer Science at Peking University; Zhejiang Lab, Zhejiang University

Abstract:

Precise congestion prediction from a placement solution plays a crucial role in circuit placement. This work proposes the lattice hypergraph (LH-graph), a novel graph formulation for circuits, which preserves netlist data during the whole learning process, and enables the congestion information propagated geometrically and topologically. Based on the formulation, we further developed a heterogeneous graph neural network architecture LHNN, jointing the routing demand regression to support the congestion spot classification. LHNN constantly achieves more than 35% improvements compared with U-nets and Pix2Pix on the F1 score. We expect our work shall highlight essential procedures using machine learning for congestion prediction.

 

 

 

 

2022 DAC

Towards Collaborative Intelligence routability Estimation based on Decentralized Private Data

Author: Jingyu Pan, Chen-Chia Chang, Zhiyao Xie, Ang Li, Minxue Tang, Tunhou Zhang, Jiang Hu, Yiran Chen

Affiliation: Duke University; Hong Kong University of Science and Technology; Texas A&M University

Abstract:

Applying machine learning (ML) in design flow is a popular trend in Electronic Design Automation (EDA) with various applications from design quality predictions to optimizations. Despite its promise, which has been demonstrated in both academic researches and industrial tools, its effectiveness largely hinges on the availability of a large amount of high-quality training data. In reality, EDA developers have very limited access to the latest design data, which is owned by design companies and mostly confidential. Although one can commission ML model training to a design company, the data of a single company might be still inadequate or biased, especially for small companies. Such data availability problem is becoming the limiting constraint on future growth of ML for chip design. In this work, we propose an Federated-Learning based approach for well-studied ML applications in EDA. Our approach allows an ML model to be collaboratively trained with data from multiple clients but without explicit access to the data for respecting their data privacy. To further strengthen the results, we co-design a customized ML model FLNet and its personalization under the decentralized training scenario. Experiments on a comprehensive dataset show that collaborative training improves accuracy by 11% compared with individual local models, and our customized model FLNet significantly outperforms the best of previous routability estimators in this collaborative training flow.

 

 

 

 

2022 ICCD

Pin Accessibility and routing Congestion Aware DRC Hotspot Prediction Using Graph Neural Network and U-Net

Author: Kyeonghyeon Baek, Hyunbum Park, Suwan Kim, Kyumyung Choi, Taewhan Kim

Affiliation: Department of Electrical and Computer Engineering, Seoul National University, Seoul, Korea

Abstract:

An accurate DRC (design rule check) hotspot prediction at the placement stage is essential in order to reduce a substantial amount of design time required for the iterations of placement and routing. It is known that for implementing chips with advanced technology nodes, (1)pin accessibilityand (2)routing congestionare two major causes of DRVs (design rule violations). Though many ML (machine learning) techniques have been proposed to address this prediction problem, it was not easy to assemble the aggregate data on items 1 and 2 in a unified fashion for training ML modes, resulting in a considerable accuracy loss in DRC hotspot prediction. This work overcomes this limitation by proposing a novel ML based DRC hotspot prediction technique, which is able to accurately capture the combined impact of items 1 and 2 on DRC hotspots. Precisely, we devise a graph, calledpin proximity graph, that effectively modes the spatial information on cell I/O pins and the information on pin-to-pin disturbance relation. Then, we propose a new ML mode, called PGNN, which tightly combines GNN (graph neural network) and U-net in a way that GNN is used to embed pin accessibility information abstracted from our pin proximity graph while U-net is used to extract routing congestion information from grid-based features. Through experiments with a set of benchmark designs using Nangate 15nm library, our PGNN outperforms the existing ML modes on all benchmark designs, achieving on average 7.8~12.5% improvements on F1-score while taking 5.5× fast inference time in comparison with that of the state-of-the-art techniques.

 

 

 

 

2021 ICCD

Automatic routability Predictor Development Using Neural Architecture Search

Author: Chen-Chia Chang, Jingyu Pan, Tunhou Zhang, Zhiyao Xie, Jiang Hu, Weiyi Qi, Chung-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen

Affiliation: National Taiwan University, Taipei, TW; Cadence, TX, USA; Texas A&M University, College Station, TX, USA; Duke University, Durham, NC, USA

Abstract:

The rise of machine learning technology inspires a boom of its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs. However, manually crafted machine learning modes require extensive human expertise and tremendous engineering efforts. In this work, we leverage neural architecture search (NAS) to automate the development of high-quality neural architectures for routability prediction, which can help to guide cell placement toward routable solutions. Our search method supports various operations and highly flexible connections, leading to architectures significantly different from all previous human-crafted modes. Experimental results on a large dataset demonstrate that our automatically generated neural architectures clearly outperform multiple representative manually crafted solutions. Compared to the best case of manually crafted modes, NAS-generated modes achieve 5.85% higher Kendall'sTin predicting the number of nets with DRC violations and 2.12% better area under ROC curve (ROC-AUC) in DRC hotspot detection. Moreover, compared with human-crafted modes, which easily take weeks to develop, our efficient NAS approach finishes the whole automatic search process with only 0.3 days.

 

 

 

 

2021 ICCAD

RouteNet Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network

Author: Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu

Affiliation: Duke Univeristy, Durham, NC, USA; National Taiwan University of Science and Technology, Taipei, TW; Nvidia Corporation, Austin, TX, USA; Texas A&M University, College Station, TX, USA

Abstract:

Early routability prediction helps designers and tools perform preventive measures so that design rule violations can be avoided in a proactive manner. However, it is a huge challenge to have a predictor that is both accurate and fast. In this work, we study how to leverage convolutional neural network to address this challenge. The proposed method, called RouteNet, can either evaluate the overall routability of cell placement solutions without global routing or predict the locations of DRC (Design Rule Checking) hotspots. In both cases, large macros in mixed-size designs are taken into consideration. Experiments on benchmark circuits show that RouteNet can forecast overall routability with accuracy similar to that of global router while using substantially less runtime. For DRC hotspot prediction, RouteNet improves accuracy by 50% compared to global routing. It also significantly outperforms other machine learning approaches such as support vector machine and logistic regression.

 

 

 

 

2021 ICCAD

Automatic routability Predictor Development Using Neural Architecture Search

Author: Chen-Chia Chang, Jingyu Pan, Tunhou Zhang1Zhiyao Xie, Jiang Hu, Weiyi Qi,Chun-Wei Lin, Rongjian Liang, Joydeep Mitra, Elias Fallon, Yiran Chen

Affiliation: Duke University, Durham, NC, USA;Texas A&M University, College Station, TX, USA;Cadence, TX, USA; 4National Taiwan University, Taipei, TW

Abstract:

The rise of machine learning technology inspires a boom of its applications in electronic design automation (EDA) and helps improve the degree of automation in chip designs. However, manually crafted machine learning models require extensive human expertise and tremendous engineering efforts. In this work, we leverage neural architecture search (NAS) to automate the development of high-quality neural architectures for routability prediction, which can help to guide cell placement toward routable solutions. Our search method supports various operations and highly flexible connections, leading to architectures significantly different from all previous human-crafted models. Experimental results on a large dataset demonstrate that our automatically generated neural architectures clearly outperform multiple representative manually crafted solutions. Compared to the best case of manually crafted models, NAS-generated models achieve 5.85% higher Kendall's T in predicting the number of nets with DRC violations and 2.12% better area under ROC curve (ROC-AUC) in DRC hotspot detection. Moreover, compared with human-crafted models, which easily take weeks to develop, our efficient NAS approach finishes the whole automatic search process with only 0.3 days.

 

 

 

 

2020 ICCAD

PROS A Plug-in for routability Optimization applied in the State-of-the-art commercial EDA Tool Using Deep Learning

Author: Jingsong Chen,Jian Kuang,Guowei Zhao,Dennis J.-H. Huang,Evangeline F. Y. Young

Affiliation: The Chinese University of Hong Kong, Cadence Design Systems

Abstract:

Recently the topic of routability optimization with prior knowledge obtained by machine learning techniques has been widely studied. However, limited by the prediction accuracy, the predictors of the existing related works can hardly be applied in a real-world EDA tool without extra runtime overhead for feature preparation. In this paper, we revisit this topic and propose a practical plug-in for routability optimization named PROS which can be applied in the state-of-the-art commercial EDA tool with negligible runtime overhead. PROS consists of an effective fully convolutional network (FCN) based predictor that only utilizes the data from placement result to forecast global routing (GR) congestion and a parameter optimizer that can reasonably adjust GR cost parameters based on prediction result to generate a better GR solution for detailed routing. Experiments on 19 industrial designs in advanced technology node show that PROS can achieve high accuracy of GR congestion prediction and significantly reduce design rule checking (DRC) violations by 11.65% on average.

 

 

 

 

2018 ISNE

Evaluation of Routability-driven Macro Placement with Machine-learning Technique

Author: Wei-Kai Cheng , Yu-Yin Guo , Chih-Shuan Wu

Affiliation: Department of Information and Computer Engineering ;Chung Yuan Christian University Taoyuan City, Taiwan

Abstract:

Macro placement is an important step in floor-plan. Macros' location directly affects the next steps, cells placement and wires routing. However, it is a time-consuming work to evaluate macro placement's result. To address this problem, we propose an effective evaluation method with machine learning technique. Our methodology predicts HPWL and routing congestion after macro placement, rather than after cells placement and global routing. Therefore, it takes much short time that we can get HPWL and routing congestion. Experiment results show that our evaluation is accurate and effective.

 

 

 

 

2018 ICCAD

RouteNet Routability Prediction for Mixed-Size Designs Using Convolutional Neural Network

Author: Zhiyao Xie, Yu-Hung Huang, Guan-Qi Fang, Haoxing Ren, Shao-Yun Fang, Yiran Chen, Jiang Hu

Affiliation: Duke Univeristy, Durham, NC, USA;National Taiwan University of Science and Technology, Taipei, TW;Nvidia Corporation, Austin, TX, USA;Texas A&M University, College Station, TX, USA

Abstract:

Early routability prediction helps designers and tools perform preventive measures so that design rule violations can be avoided in a proactive manner. However, it is a huge challenge to have a predictor that is both accurate and fast. In this work, we study how to leverage convolutional neural network to address this challenge. The proposed method, called RouteNet, can either evaluate the overall routability of cell placement solutions without global routing or predict the locations of DRC (Design Rule Checking) hotspots. In both cases, large macros in mixed-size designs are taken into consideration. Experiments on benchmark circuits show that RouteNet can forecast overall routability with accuracy similar to that of global router while using substantially less runtime. For DRC hotspot prediction, RouteNet improves accuracy by 50% compared to global routing. It also significantly outperforms other machine learning approaches such as support vector machine and logistic regression.

 

 

 

 

2016 ICCD

BEOL Stack Aware Routability Prediction From Placement Using Data Mining Techniques

Author: Wei-Ting J. Chan, Yang Du&, Andrew B. Kahng,Siddhartha Nath,Kambiz Samadi

Affiliation: CSE and ECE Departments, UC San Diego

Abstract:

Optimizations at placement stage need to be guided by timing estimation prior to routing. To handle timing uncertainty due to the lack of routing information, people tend to make very pessimistic predictions such that performance specification can be ensured in the worst case. Such pessimism causes over-design that wastes chip resources or design effort. In this work, a machine learning-based pre-routing timing prediction approach is introduced. Experimental results show that it can reach accuracy near post-routing sign-off analysis. Compared to a commercial pre-routing timing estimation tool, it reduces false positive rate by about 2/3 in reporting timing violations.

 

 

 

 

2014 ICCD

Accurate Prediction of Detailed routing Congestion Using Supervised Data Learning

Author: Zhongdong Qi,Yici Cai,Qiang Zhou

Affiliation: Computer Science Department ,Tsinghua University,Beijing, China

Abstract:

Routing congestion mode is of great importance in design stages of modern physical synthesis, e.g. global routing and routability estimation during placement. As the technology node becomes smaller, routing congestion is more difficult to estimate during design stages ahead of detailed routing. In this paper, we propose a framework using nonparametric regression technique in machine learning to construct routing congestion mode. The constructed mode can capture multiple factors and enables direct prediction of detailed routing congestion with high accuracy. By using this mode in global routing, significant reduction of design rule violations and detailed routing runtime can be achieved

compared with the mode in previous work, with small overhead in global routing runtime and memory usage.

 

 

 

 

AI+EDA

Routability prediction