2024 DAC

ChatCPU: An Agile CPU Design and Verification Platform with LLM

Author: Xi Wang; Gwok-Waa Wan ; Sam-Zaak Wong; Layton Zhang; Tianyang Liu ; Qi Tian ; Jianmin Ye

Affiliation: Southeast University & National Center of Technology Innovation for EDA; National Center of Technology Innovation for EDA; Southeast University

Abstract:

The increasing complexity of semiconductor designs necessitates agile hardware development methodologies to keep pace with rapid technological advancements. Following this trend, Large Language Models (LLMs) emerge as a potential solution, providing new opportunities in hardware design automation. However, existing LLMs exhibit challenges in HDL design and verification, especially for complicated hardware systems. Addressing this need, we introduce ChatCPU, the first end-to-end agile hardware design and verification platform with LLM. ChatCPU streamlines the ASIC design and verification process, guiding it from initial specifications to the final RTL implementations with enhanced design agility. Incorporating the LLM fine-tuning and the processor description language design for CPU design automation, ChatCPU significantly enhances the hardware design capability using LLM. Utilizing ChatCPU, we developed a 6-stage in-order RISC-V CPU prototype, achieving successful tape-out using SkyWater 130nm MPW project with Efabless, which is currently the largest CPU design generated by LLM. Our results demonstrate a remarkable improvement in CPU design efficiency, accelerating the design iteration process by an average of 3.81X, and peaking at 12X and 9.33X in HDL implementations and verification stages, respectively. The ChatCPU also enhances the design capability of LLM by 2.63X as compared to base LLama2. These advancements position ChatCPU as a significant milestone in LLM-driven ASIC design and verification.

 

 

 

 

2024 ASP-DAC

DeepIC3: Guiding IC3 Algorithms by Graph Neural Network Clause Prediction

Author: Jianheng Tang, Wei Zhang

Affiliation: The Hong Kong University of Science and Technology

Abstract:

In recent years, machine learning has demonstrated its potential in many challenging problems. In this paper, we extend its use to hardware formal property verification and propose DeepIC3, a method that takes advantage of graph learning in the classic IC3/PDR algorithm. In DeepIC3, graph neural networks are integrated to improve the result of local inductive generalization. This helps provide a global view of the state transition system and can potentially lead the algorithm out of local optima in the search of inductive invariants. Our experiments demonstrate that DeepIC3 accelerates the vanilla algorithm in nontrivial test cases of hardware mode checking competition benchmarks (HWMCC2020) with up to 10.8x speed-up. The proposed machine-learning integration preserves soundness and is universally applicable to various IC3/PDR implementations.

 

 

 

 

2024 ASP-DAC

Hardware Phi-1.5B: A Large Language Mode Encodes Hardware Domain Specific Knowledge

Author: Yier Jin, Xiaolong Guo, Raj Dutta; Weimin Fu, Yifang Zhao, Kaichen Yang,  Haocheng Ma

Affiliation: Kansas State University, University of Science and Technology of China, Tianjin University

Abstract:

In the rapidly evolving semiconductor industry, where research, design, verification, and manufacturing are intricately linked, the potential of Large Language modes to revolutionize hardware design and security verification is immense. The primary challenge, however, lies in the complexity of hardware-specific issues that are not adequately addressed by the natural language or software code knowledge typically acquired during the pretraining stage. Additionally, the scarcity of datasets specific to the hardware domain poses a significant hurdle in developing a foundational mode. Addressing these challenges, this paper introduces Hardware Phi-1.5B, an innovative large language mode specifically tailored for the hardware domain of the semiconductor industry. We have developed a specialized, tiered dataset comprising small, medium, and large subsets and focused our efforts on pre-training using the medium dataset. This approach harnesses the compact yet efficient architecture of the Phi-1.5B mode. The creation of this first pre-trained, hardware domain-specific large language mode marks a significant advancement, offering improved performance in hardware design and verification tasks and illustrating a promising path forward for AI applications in the semiconductor sector.

 

 

 

 

2024 ARXIV

AssertLLM: Generating and Evaluating Hardware Verification Assertions from Design Specifications via Multi-LLMs

Author: Wenji Fang, Mengming Li, Min Li, Zhiyuan Yan, Shang Liu, Hongce Zhang, and Zhiyao Xie.

Affiliation: Hong Kong University of Science and Technology, Hong Kong University of Science and Technology (Guangzhou)

Abstract:

Assertion-based verification (ABV) is a critical method for ensuring design circuits comply with their architectural specifications, which are typically described in natural language. This process often requires significant interpretation by engineers to convert these specifications into functional verification assertions. Existing methods for generating assertions from natural language specifications are limited to sentences extracted by engineers, discouraging the practical application. In this work, we present AssertLLM, an automatic assertion generation framework for complete specification files. AssertLLM breaks down the complex task into three phases, incorporating three customized Large Language modes (LLMs) for extracting structural specifications, mapping signal definitions, and generating assertions. Additionally, we provide an open-source benchmark for assessing assertion generation capabilities. Our evaluation of AssertLLM on a full design, encompassing 23 signals, demonstrates that 89% of the generated assertions are both syntactically and functionally accurate.

 

 

 

 

2023 ASPLOS

RepCut: Superlinear Parallel RTL Simulation with Replication-Aided Partitioning

Author: Haoyuan Wang, Scott Beamer

Affiliation: University of California at Santa Cruz, Santa Cruz, USA

Abstract:

Register transfer level (RTL) simulation is an invaluable tool for developing, debugging, verifying, and validating hardware designs. Despite the parallel nature of hardware, existing parallel RTL simulators yield speedups unattractive for practical application due to high communication and synchronization costs incurred by typical circuit topologies. We present RepCut, a novel parallel RTL simulation methodology. RepCut is enabled by our replication-aided partitioning approach that cuts the circuit into balanced partitions with small overlaps. By replicating the overlaps, RepCut eliminates problematic data dependences between partitions and significantly reduces expensive synchronization overhead between parallel threads. RepCut outperforms state-of-the-art simulators, and when simulating a large system-on-chip with multiple out-of-order cores, it achieves a 27.10× speedup (superlinear) using 24 threads with only a 3.81% replication cost.

 

 

 

 

2023 DAC

Late Breaking Results: Test Selection for RTL Coverage by Unsupervised Learning from Fast Functional Simulation

Author: Rongjian Liang, Nathaniel Ross Pinckney, Yuji Chai, Haoxin Ren, Brucek Khailany

Affiliation: Dept. Computer Science, Harvard University, Cambridge, US; NVIDIA, Austin, US

Abstract:

Functional coverage closure is an important but RTL simulation intensive aspect of constrained random verification. To reduce these computational demands, we propose test selection for functional coverage via machine learning (ML) based anomaly detection in the structural coverage space of fast functional simulators. We achieve promising results on two units from a state-of-the-art production GPU design. With our approach, an up to 85% RTL simulation runtime reduction can be achieved when compared to baseline constrained random test selection while achieving the same RTL functional coverage.

 

 

 

 

2023 ARXIV

Using LLMs to Facilitate Formal Verification of RTL

Author: Marcelo Orenes-Vera, Margaret Martonosi, and David Wentzlaff

Affiliation: Department of Computer Science and Electrical Engineering, Princeton University Princeton, New Jersey, USA

Abstract:

Formal property verification (FPV) has existed for decades and has been shown to be effective at finding intricate RTL bugs. However, formal properties, such as those written as SystemVerilog Assertions (SVA), are time-consuming and error-prone to write, even for experienced users. Prior work has attempted to lighten this burden by raising the abstraction level so that SVA is generated from high-level specifications. However, this does not eliminate the manual effort of reasoning and writing about the detailed hardware behavior. Motivated by the increased need for FPV in the era of heterogeneous hardware and the advances in large language modes (LLMs), we set out to explore whether LLMs can capture RTL behavior and generate correct SVA properties.

First, we design an FPV-based evaluation framework that measures the correctness and completeness of SVA. Then, we evaluate GPT4 iteratively to craft the set of syntax and semantic rules needed to prompt it toward creating better SVA. We extend the open-source AutoSVA framework by integrating our improved GPT4-based flow to generate safety properties, in addition to facilitating their existing flow for liveness properties. Lastly, our use cases evaluate (1) the FPV coverage of GPT4-generated SVA on complex open-source RTL and (2) using generated SVA to prompt GPT4 to create RTL from scratch.

Through these experiments, we find that GPT4 can generate correct SVA even for flawed RTL, without mirroring design errors. Particularly, it generated SVA that exposed a bug in the RISC-V CVA6 core that eluded the prior work's evaluation.

 

 

 

 

2022 ASPLOS

CirFix: Automatically Repairing Defects in Hardware Design Code

Author: Hammad Ahmad, Yu Huang, Westley Weimer

Affiliation: University of Michigan, USA

Abstract:

This paper presents CirFix, a framework for automatically repairing defects in hardware designs implemented in languages like Verilog. We propose a novel fault localization approach based on assignments to wires and registers, and a fitness function tailored to the hardware domain to bridge the gap between software-level automated program repair and hardware descriptions. We also present a benchmark suite of 32 defect scenarios corresponding to a variety of hardware projects. Overall, CirFix produces plausible repairs for 21/32 and correct repairs for 16/32 of the defect scenarios. This repair rate is comparable to that of successful program repair approaches for software, indicating CirFix is effective at bringing over the benefits of automated program repair to the hardware domain for the first time.

 

 

 

 

2022 DAC

Design-while-Verify: Correct-by-Construction Control Learning with Verification in the Loop

Author: Yixuan Wang, Chao Huang, Zhaoran Wang, Zhilu Wang, Qi Zhu

Affiliation: Northwestern University, USA, Liverpool University, UK

Abstract:

In the current control design of safety-critical cyber-physical systems, formal verification techniques are typically appliedafterthe controller is designed to evaluate whether the required properties (e.g., safety) are satisfied. However, due to the increasing system complexity and the fundamental hardness of designing a controller with formal guarantees, such an open-loop process ofdesign-then-verifyoften results in many iterations and fails to provide the necessary guarantees. In this paper, we propose a correct-by-construction control learning framework that integrates the verification into the control design process in a closed-loop manner, i.e.,design-while-verify.Specifically, we leverage the verification results (computed reachable set of the system state) to construct feedback metrics for control learning, which measure how likely the current design of control parameters can meet the required reach-avoid property for safety and goal-reaching. We formulate an optimization problem based on such metrics for tuning the controller parameters, and develop an approximated gradient descent algorithm with a difference method to solve the optimization problem and learn the controller. The learned controller is formally guaranteed to meet the required reach-avoid property. By treating verifiability as a first-class objective and effectively leveraging the verification results during the control learning process, our approach can significantly improve the chance of finding a control design with formal property guarantees, demonstrated in a set of experiments that use mode-based or neural network based controllers.

 

 

 

 

2021 ICCAD

Graph Learning-Based Arithmetic Block Identification

Author: Zhuolun He, Ziyi Wang, Chen Bai, Haoyu Yang, Bei Yu

Affiliation: The Chinese University of Hong Kong, NVIDIA

Abstract:

Arithmetic block identification in gate-level netlist is an essential procedure for malicious logic detection, functional verification, or macro-block optimization. We argue that existing methods suffer either scalability or performance issues. To address the problem, we propose a graph learning-based solution that promises to extract desired logic components from a complete design netlist. We further design a novel asynchronous bidirectional graph neural network (ABGNN) dedicated to representation learning on directed acyclic graphs. Experimental results on open-source RISC-V CPU designs demonstrate that our proposed solution significantly outperforms several state-of-the-art arithmetic block identification flows.

 

 

 

 

2021 NeurIPS

Learning Semantic Representations to Verify Hardware Designs

Author: Shobha Vasudevan, Wenjie Jiang, David Bieber, Rishabh Singh, Hamid Shojaei, Richard Ho

Affiliation: Google Research, Brain Team

Abstract:

Verification is a serious bottleneck in the industrial hardware design cycle, routinely requiring person-years of effort. Practical verification relies on a “best effort” process that simulates the design on test inputs. This suggests a new research question: Can this simulation data be exploited to learn a continuous representation of a hardware design that allows us to predict its functionality? As a first approach to this new problem, we introduce Design2Vec, a deep architecture that learns semantic abstractions of hardware designs. The key idea is to work at a higher level of abstraction than the gate or the bit level, namely the Register Transfer Level (RTL), which is similar to software source code, and can be represented by a graph that incorporates control and data flow. This allows us to learn representations of RTL syntax and semantics using a graph neural network. We apply these representations to several tasks within verification, including predicting what cover points of the design will be covered (simulated) by a test, and generating new tests to cover desired cover points. We evaluate Design2Vec on three real-world hardware designs, including the TPU, Google’s industrial chip used in commercial data centers. Our results demonstrate that Design2Vec dramatically outperforms baseline approaches that do not incorporate the RTL semantics and scales to industrial designs. It generates tests that cover design points that are considered hard to cover with manually written tests by design verification experts in a fraction of the time.

 

 

 

 

2018 GLVLSI

Accelerating Coverage Directed Test Generation for Functional Verification: A Neural Network-Based Framework

Author: Fanchao Wang, Hanbin Zhu, Pranjay Popli, Yao Xiao, Paul Bogdan, and Shahin Nazarian

Affiliation: University of Southern California, Los Angeles, CA, USA

Abstract:

With increasing design complexity, the correlation between test transactions and functional properties becomes non-intuitive, hence impacting the reliability of test generation. This paper presents a modified coverage directed test generation based on an Artificial Neural Network (ANN). The ANN extracts features of test transactions and only those which are learned to be critical, will be sent to the design under verification. Furthermore, the priority of coverage groups is dynamically learned based on the previous test iterations. With ANN-based screening, low-coverage or redundant assertions will be filtered out, which helps accelerate the verification process. This allows our framework to learn from the results of the previous vectors and use that knowledge to select the following test vectors. Our experimental results confirm that our learning-based framework can improve the speed of existing function verification techniques by 24.5x and also also deliver assertion coverage improvement, ranging from 4.3x to 28.9x, compared to traditional coverage directed test generation, implemented in UVM.

 

 

 

 

2016 ICCAD

BugMD: Automatic Mismatch Diagnosis for Bug Triaging

Author: Biruk Mammo, Milind Furia, Valeria Bertacco, Scott A. Mahlke, and Daya Shanker Khudia

Affiliation: University of Michigan, Ann Arbor, MI, USA

Abstract:

System-level validation is the most challenging phase of design verification. A common methodology in this context entails simulating the design under validation in lockstep with a high-level golden mode, while comparing the architectural state of the two modes at regular intervals. However, if a bug is detected, the diagnosis of the problem with this framework is extremely time and resource consuming. To address this challenge, we propose a novel bug triaging solution that collects multiple architectural-level mismatches and employs a classifier to pinpoint buggy design units. We also design and implement an automated synthetic bug injection framework that enables us to generate large datasets for training our classifier modes. Experimental results show that our solution is able to correctly identify the source of a bug over 70% of the time in an out-of-order processor mode. Furthermore, our solution can identify the top 3 most likely units with over 90% accuracy.

 

 

 

 

2014 ICCAD

On Application of Data Mining in Functional Debug

Author: Kuo-Kai Hsieh, Wen Chen, Li-C. Wang, and Jayanta Bhadra

Affiliation: Department of Electrical and Computer Engineering, University of California, Santa Barbara, Technology Solution Organization, Freescale Semiconductor Inc.

Abstract:

This paper investigates how data mining can be applied in functional debug, which is formulated as the problem of explaining a functional simulation error based on human-understandable machine states. We present a rule discovery methodology comprising two steps. The first step selects relevant state variables for constructing the mining dataset. The second step applies rule learning to extract rules that differentiates the tests that excite error behavior from those that do not. We explain the dependency of the second step on the first step and considerations for implementing the methodology in practice. Application of the proposed methodology is illustrated through experiments conducted on a recent commercial SoC design.

 

 

 

 

2012 ICCAD

Novel Test Detection to Improve Simulation Efficiency—A Commercial Experiment

Author: Wen Chen, Nik Sumikawa, Li-C. Wang, Jayanta Bhadra, Xiushan Feng, and Magdy S. Abadir

Affiliation: University of California, Santa Barbara, USA, Freescale Semiconductor Inc., USA

Abstract:

Novel test detection is an approach to improve simulation efficiency by selecting novel tests before their application [1]. Techniques have been proposed to apply the approach in the context of processor verification [2]. This work reports our experience in applying the approach to verifying a commercial processor. Our objectives are threefold: to implement the approach in a practical setting, to assess its effectiveness and to understand its challenges in practical application. The experiments are conducted based on a simulation environment for verifying a commercial dual-thread low-power processor core. By focusing on the complex fixed-point unit, the results show up to 96% saving in simulation time. The main limitation of the implementation is discussed based on the load-store unit with initial promising results to show how to overcome the limitation.

 

 

 

 

2011 DAC

Learning Microarchitectural Behaviors to Improve Stimuli Generation Quality

Author: Yoav Katz, Michal Rimon, Avi Ziv, and Gai Shaked

Affiliation: IBM Research, Haifa, Haifa, Israel, Computer Science Department, Technion-Israel Institute of Technology, Haifa, Israel

Abstract:

Microarchitectural information regarding various aspects of instruction execution can help processor-level stimuli generators more easily reach verification goals. While many such aspects are based on common microarchitectural concepts, their specific manifestations are highly design-specific. We propose using an automatic method for acquiring such microarchitectural knowledge and integrating it into the stimuli generator. We start by extracting microarchitectural data from simulation traces. This data is fed to a decision tree learning algorithm that produces rules for microarchitectural behavior of instructions; these rules are then integrated into the testing knowledge of the stimuli generator. This testing knowledge can provide users with the ability to better control the microarchitectural behavior of generated instructions, leading to higher quality test cases. Experimental results on the POWER7 processor showed that our proposed method can improve the microarchitectural coverage of the design.

 

 

 

 

2011 DAC

Learning Microarchitectural Behaviors to Improve Stimuli Generation Quality

Author: Yoav Katz, Michal Rimon, Avi Ziv, Gai Shaked

Affiliation: IBM Research, Haifa, Haifa, Israel, Computer Science Department, Technion-Israel Institute of Technology, Haifa, Israel

Abstract:

Microarchitectural information regarding various aspects of instruction execution can help processor-level stimuli generators more easily reach verification goals. While many such aspects are based on common microarchitectural concepts, their specific manifestations are highly design-specific. We propose using an automatic method for acquiring such microarchitectural knowledge and integrating it into the stimuli generator. We start by extracting microarchitectural data from simulation traces. This data is fed to a decision tree learning algorithm that produces rules for microarchitectural behavior of instructions; these rules are then integrated into the testing knowledge of the stimuli generator. This testing knowledge can provide users with the ability to better control the microarchitectural behavior of generated instructions, leading to higher quality test cases. Experimental results on the POWER7 processor showed that our proposed method can improve the microarchitectural coverage of the design.

 

 

 

 

2008 DAC

Functional Test Selection Based on Unsupervised Support Vector Analysis

Author: Onur Guzey, Li-C. Wang, Jeremy R. Levitt, and Harry Foster

Affiliation: University of Southern California, Los Angeles, CA, USA

Abstract:

Extensive software-based simulation continues to be the mainstream methodology for functional verification of designs. To optimize the use of limited simulation resources, coverage metrics are essential to guide the development of effective test suites. Traditional coverage metrics are defined based on either a functional mode or a structural mode of the design. If our goal is to select a subset of tests from a set of tests, using these coverage metrics require simulation of the entire set before the effectiveness of tests can be compared. In this paper, we propose a novel methodology that estimates the input space covered by a set of tests. We use unsupervised support vector analysis to learn such a space, resulting in a subset of tests that represent the original set of tests. A direct application of this methodology is to select tests before simulation in order to reduce simulation cycles. Consequently, simulation effectiveness can be improved. Experimental results based on application of the proposed methodology to the OpenSparc T1 processor are reported to demonstrate the practicality of our approach.

 

 

 

 

2008 ATS

Coverage Directed Test Generation: Godson Experience

Author: Haihua Shen, Wenli Wei, Yunji Chen, Bowen Chen, and Qi Guo

Affiliation: Institute of Computing Technology, Chinese Academy and Sciences, Beijing, China

Abstract:

Biased random test generation is one of the most important methods for the verification of modern complex processors. As the complexity of processors grows, the bottleneck remains in generating suitable test programs that meet coverage metrics automatically. Many technologies have been proposed to implement the automatic feedback loop. In this paper, we introduce our coverage directed test generation scheme which combines traditional biased random test generation and genetic algorithms to feed back process. It is the first time we use our scheme in our real industrial processor verification independently and successfully without human intervention. The efficiency of our approach has been demonstrated by the practical results.

 

 

 

 

2008 ASP-DAC

RTL Regression Test Selection using Machine Learning

Author: Ganapathy Parthasarathy, Aabid Rushdi, Parivesh Choudhary, Saurav Nanda, Malan Evans, Hansika Gunasekara, Sridhar Rajakumar

Affiliation: Synopsys Inc., Mountain View, CA

Abstract:

Regression testing is a technique to ensure that micro-electronic circuit design functionality is correct under iterative changes during the design process. This incurs significant costs in the hardware design and verification cycle in terms of productivity, machine and simulation software costs, and time - sometimes as much as 70% of the hardware design costs. We propose a machine learning approach to select a subset of tests from the set of all RTL regression tests for the design. Ideally, the selected subset should detect all failures that the full set of tests would have detected. Our approach learns characteristics of both RTL code and tests during the verification process to estimate the likelihood that a test will expose a bug introduced by an incremental design modification. This paper describes our approach to the problem and its implementation. We also present experiments on several real-world designs of various types with different types of test-suites that demonstrate significant time and resource savings while maintaining validation quality.

 

 

 

 

2007 TCAD

Microprocessor Verification via Feedback-Adjusted Markov Modes

Author: Ilya Wagner, Valeria Bertacco, and Todd M. Austin

Affiliation: University of Michigan, Ann Arbor, MI, USA

Abstract:

The challenge of verifying a modern microprocessor design is an overwhelming one: Increasingly complex microarchitectures combined with heavy time-to-market pressure have forced microprocessor vendors to employ immense verification teams in the hope of finding the most critical bugs in a timely manner. Unfortunately, too often, size does not seem to matter in verification, as design schedules continue to slip and microprocessors find their way to the marketplace with design errors. In this paper, we describe a novel closed-loop simulation-based approach to hardware verification and present a tool called StressTest that uses our methods to locate hard-to-find corner-case design bugs and performance problems. StressTest is based on a Markov-mode-driven random instruction generator with activity monitors. The mode is generated from the user-specified template files and is used to generate the instructions sent to the design under test (DUT). In addition, the user specifies key activity nodes within the design that should be stressed and monitored throughout the simulation. The StressTest engine then uses closed-loop feedback techniques to transform the Markov mode into one that effectively stresses the user-selected points of interest. In parallel, StressTest monitors the correctness of the DUT response and, if the design behaves against expectation, it reports a bug and a trace leading to it. Using two microarchitectures as example testbeds, we demonstrate that StressTest finds more bugs with less effort than open-loop random instruction test generation techniques.

 

 

 

 

2006 DATE

Efficient Assertion Based Verification using TLM

Author: Ali Habibi, Sofiène Tahar, Amer Samarah, Donglin Li, and Otmane Aït Mohamed

Affiliation: Department of Electrical and Computer Engineering, Concordia University, Montreal, QUE, Canada

Abstract:

Recent advancement in hardware design urge during a transaction based mode as a new intermediate design level. Supporters for the Transaction Level modeing (TLM) trend claim its efficiency in terms of rapid prototyping and fast simulation incomparison to the classical RTL-based approach. Intuitively, from a verification point of view, faster simulation induces better coverage results. This is driven by two factors: coverage measurement and simulation guidance. In this paper, we propose to use an abstract mode of the design, written in the Abstract State Machines Language(AsmL), in order to provide an adequate way for measuring the functional coverage. Then, we use this metric indefining the fitness function of a genetic algorithm proposed to improve the simulation efficiency. Finally, we compare our coverage and simulation results to:(1) random simulation at TLM; and (2) the Specman tool of Verisityat RTL.

 

 

 

 

2006 ILP

Towards Automating Simulation-based Design Verification using ILP

Author: Kerstin Eder, Peter A. Flach, and Hsiou-Wen Hsueh

Affiliation: Department of Computer Science, University of Bristol

Abstract:

Increasing the productivity of simulation-based semiconductor design verification is one of the urgent challenges identified in the International Technology Roadmap for Semiconductors. The most difficult aspect is the generation of stimulus for functional coverage closure. This paper introduces a new Coverage-Directed test Generation (CDG) feedback loop which applies Inductive Logic Programming (ILP) to selected tests and coverage data to induce rules that can be used to automatically direct stimulus generation towards outstanding coverage. The case study documented in this paper shows a significant reduction of simulation time when ILP-based CDG is compared to random test generation. This is an exciting and promising new application area for ILP.

 

 

 

 

2003 DAC

Coverage Directed Test Generation for Functional Verification using Bayesian Networks

Author: Shai Fine, Avi Ziv

Affiliation: IBM Research Laboratory, Haifa, Israel

Abstract:

Functional verification is widely acknowledged as the bottleneckin the hardware design cycle.This paper addresses one of themain challenges of simulation based verification (or dynamic veri-fication), by providing a new approach for Coverage Directed TestGeneration (CDG). This approach is based on Bayesian networksand computer learning techniques. It provides an efficient way forclosing a feedback loop from the coverage domain back to a gener-ator that produces new stimuli to the tested design. In this paper, weshow how to apply Bayesian networks to the CDG problem. Ap-plying Bayesian networks to the CDG framework has been tested inseveral experiments, exhibiting encouraging results and indicatingthat the suggested approach can be used to achieve CDG goals.

 

 

 

 

 

AI+EDA

Verification, simulation, and debug