Abstract: 

   With increasing system complexity together with stringent runtime requirements for functional safety, the reliable and secure operation of electronics in safety-critical, enterprise servers and cloud computing domains become even more challenging. This is further exacerbated with nanoscale effects originating from new device structures and complex fabrication processes in advanced nodes. While traditionally design time and test time solutions were supposed to guarantee the in-field dependability and security of electronic systems, due to complex interaction of runtime effects from running workload and environment, there is a great need for a holistic approach for silicon lifecycle management, spanning from design time to in-field monitoring and adaptation.  This talk discusses the requirements and trends, as well as the opportunities and challenges of SLM for complex chips and systems fabricated in advanced nanoscale technology nodes.

Bio:

  Mehdi B. Tahoori is Professor and the Chair of Dependable Nano-Computing at Karlsruhe Institute of Technology (KIT), Germany. He received the B.S. degree in computer engineering from Sharif University of Technology, Tehran, Iran, in 2000, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University, Stanford, CA, in 2002 and 2003, respectively. He is currently the deputy editor-in-chief of IEEE Design and Test Magazine. He was the editor-in-chief of Elsevier Microelectronic Reliability journal. He was the program and general chair of IEEE VLSI Test Symposium in (VTS) and General Chair of IEEE European Test Symposium (ETS). Prof. Tahoori was a recipient of the US National Science Foundation Early Faculty Development (CAREER) Award in 2008 and European Research Council (ERC) Advanced Grant in 2022. He has received a number of best paper nominations and awards at various conferences and journals. He is currently the chair of IEEE European Test Technologies Technical Council (eTTTC). He is a fellow of the IEEE.

01 Title: High-Performance and Energy-Efficient Edge Inference Chips and Systems for Large-Scale AI Models: The InnoHK ACCESS Approach and Story

03 Title: Subspace Derivative Free Optimization for High-dimensional Nonlinear Optimization of Analog Integrated Circuit Synthesis

Abstract: 

   The analog integrated circuit design faces the challenges of enormous circuit scale, vast design space and complex design performance. High-dimensional nonlinear optimization and high-dimensional multi-objective optimization face the challenges of high modeling complexity, curse of dimensionality and difficulty in achieving convergence in nonlinear global optimization. In this keynote speech, we will present subspace based DFO innovative approaches to address the high-dimensional optimization problems encountered in analog integrated circuit synthesis. Firstly, an efficient batch Bayesian and Gaussian process enhanced subspace derivative free optimization method (BBGP-sDFO) is presented for high-dimensional analog circuit sizing. The proposed method reduces any high-dimensional analog circuit sizing problem into an effective 2-dimensional subspace. The proposed method BBGP-sDFO achieves 2.05× ∼ 17.65× simulation number speedup and 1.37× ∼ 16.11× runtime speedup compared with the state-of-the-art optimization methods. Secondly, a novel high-dimensional multi-objective optimization method via adaptive gradient-based subspace sampling (HiMOSS) is presented. The proposed HiMOSS method integrates previous gradients and previous iterations into the adaptive subspace through multi-variate Gaussian distribution. The subspace is constructed with gradients and previous success steps with their significance decaying over iterations. Compared to multi-objective method NSGA-II, HiMOSS achieves a 2.56× ~ 4.32× simulation number speedup and a 2.48× ~3.39× total runtime speedup reaching similar hypervolume for ACCIA and OTA circuit. Compared to multi-objective method MOEA/D, the proposed method achieves 7.72× and 5.19× simulation number speedups for ACCIA and OTA circuits. The proposed HiMOSS achieves better optimization results compared to the state-of-the-art high dimensional multi-objective methods. Finally, a constrained Voronoi tree-based domain decomposition method for high-dimensional Bayesian optimization is presented. The proposed cVTS algorithm achieves 11.6 times runtime speedup compared to the state-of-the-art method, making it a promising technique for high-dimensional analog circuit design automation.

Bio:

   Xuan Zeng (Senior Member, IEEE) received the B.S. and Ph.D. degrees in electrical engineering from Fudan University, Shanghai, China, in 1991 and 1997, respectively. She was a Visiting Professor with the Department of Electrical Engineering, Texas A&M University, College Station, TX, USA, in 2002, and the Microelectronics Department, Technische Universiteit Delft, Delft, The Netherlands, in 2003. From 2008 to 2012, she was the Director of the State Key Laboratory of Application Specific Integrated Circuits (ASIC) and Systems, Fudan University, where she is currently a Full Professor with the Microelectronics Department. Her current research interests include analog circuit modeling and synthesis, design for manufacturability, high-speed interconnect analysis and optimization, and circuit simulation. Prof. Zeng received the Changjiang Distinguished Professor with the Ministry of Education Department of China in 2014, the Chinese National Science Funds for Distinguished Young Scientists in 2011, the First-Class of Natural Science Prize of Shanghai in 2012, the 10th For Women in Science Award in China in 2013, and the Shanghai Municipal Natural Science Peony Award in 2014. She also received the Best Paper Award from the 8th IEEE Annual Ubiquitous Computing, Electronics and Mobile Communication Conference 2017. She is an Associate Editor of the IEEE Transactions on Circuits and Systems—Part II: Express Briefs, the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and the ACM Transactions on Design Automation of Electronic Systems.

Abstract:

  This talk will give an overview of demands, challenges and opportunities of edge inference hardware and some highlights of the ACCESS center (https://inno-access.hk/) of the past few years, as well as the directions and challenges to address in ACCESS center for the next few years. The talk will also cover some of the EDA and test issues of edge inference hardware.

Bio: 

   Prof. Tim CHENG Kwang-Ting was appointed Vice-President for Research and Development with effect from April 1, 2022. He joined HKUST in May 2016 as the Dean of Engineering, in concurrence with his appointment as Chair Professor jointly in the Department of Electronic and Computer Engineering and in the Department of Computer Science and Engineering.

   He graduated from University of California, Berkeley in 1988 with a PhD in Electrical Engineering and Computer Sciences. Before joining HKUST, he was a Professor of Electrical and Computer Engineering (ECE) at the University of California, Santa Barbara (UCSB), where he served since 1993. Prior to teaching at UC Santa Barbara, he spent five years at AT&T Bell Laboratories.

   At UC Santa Barbara, Prof. Cheng had taken up various important academic leadership roles, such as Founding Director of the Computer Engineering Program from 1999 to 2002, Chair of Department of ECE from 2005 to 2008, Acting Associate Vice-Chancellor for Research in 2013 and Associate Vice-Chancellor for Research from 2014 to 2016 where he helped oversee the research development, infrastructure, and compliance of UCSB’s research enterprise with over US$200 million extramural research funding.

  A highly respected teacher-scholar and internationally leading researcher with excellent experience in fostering cross-disciplinary research collaboration, Prof. Cheng is a world authority in the field of electronics testing and design verification, as well as an impactful contributor across a wide range of research areas including design automation of electronic and photonic systems, computer vision, and medical image analysis. He had previously served as Director of the US Department of Defense Multidisciplinary University Research Initiative (MURI) Center for 3D Hybrid Circuits which integrated CMOS and nano-memristors for future computing systems. He has published more than 500 technical papers, co-authored five books, held 12 US patents, and transferred several of his inventions into successful commercial products. He is a Fellow of the Institute of Electrical and Electronics Engineers (IEEE) and Hong Kong Academy of Engineering Sciences (HKAES). His works are of high impact with due recognition from the field, including 12 best paper awards and one Distinguished Paper Citation in major conferences and journals, as well as a Pan Wen Yuan Foundation Award for Outstanding Research. He was also recognized in the 50th Design Automation Conference (DAC) in 2013 as a Top 10 Author in DAC’s Fourth Decade and a Prolific Author.

   Prof. Cheng has been very active in providing professional services to the IEEE and to the academic community at large. Having served as the editor-in-chief of IEEE Design & Test of Computers, on the boards of IEEE Council on Electronic Design Automation’s Board of Governors and IEEE Computer Society’s Publications Board, and on various technology advisory or working groups including the International Technology Roadmap for Semiconductors (ITRS), Prof. Cheng has been internationally known as an eminent member of the field.

   In 2020, he received HK$443.9 million funding from the Hong Kong government’s InnoHK research clusters initiative to lead the founding of the AI Chip Center for Emerging Smart Systems for which four world-renowned universities participate. The multidisciplinary center aims to advance IC design to help realize ubiquitous AI applications in society.

Kwang-Ting CHENG, HKUST, IEEE Fellow

Keynotes

04 Title: From DFT to product quality and reliability: grand challenges and innovative solutions

Junna Zhong, Siemens EDA

Abstract: 
Many safety-critical and mission-critical applications are very compute-intensive and pushing the adoption of new technology nodes. Ensuring the reliable operation of these complex systems throughout the entire lifecycle is one of the biggest challenges facing the semiconductor industry today. In this talk, we review the main challenges from DFT to product quality and reliability and present our vision on how to address them: How can we reduce test escapes in manufacturing? Can an in-system test combined with environmental monitoring achieve the required high reliability? What new DFT architectures are needed? How can these problems be solved with cost/time constraints? How and where can AI/ML help DFT and yield engineers with productivity and quality of results?

Bio:
Junna Zhong, Tessent AE Director in Siemens EDA, China. She has been engaging in Tessent product line technical works for more than 12 years, promoting and supporting Tessent DFT/DDYA related products in IC companies and foundries in China, and has accumulated rich experience in design for test and yield improvement.