TUTORIALS

Tutorial 1 (9:30-12:30, August 18)

Title: Addressing Reliability, Availability, and Serviceability (RAS) Challenges with the Power of Silicon Lifecycle Management (SLM)

Speakers: Fei Su (Intel), Jyotika Athavale (Synopsys) and Yervant Zorian (Synopsys)

           Fei Su                                              Yervant Zorian                                        Jyotika Athavale 

Abstract: 

In the AI era where emerging workloads have been driving unprecedented computing demands, Reliability, Availability, and Serviceability (RAS) are foundational for creating trustworthy computing. This tutorial will offer a broad perspective emphasizing the pressing challenges in RAS within several critical market segments. To ensure RAS of mission or safety critical systems, various innovations are needed across different layers from silicon, software to in-field system deployment at scale, as well as spanning across different stages of the entire product lifecycle. This tutorial will highlight the significance of Silicon Lifecycle Management (SLM) technologies in enhancing RAS and addressing the challenges. We expect to provide the attendees the insights into the current state and future opportunities of RAS and SLM technology innovations in the industry.

Biography (Fei Su):

Dr. Fei Su is a senior architect at Intel Corporation, leading R&D in DFX (Design for Testability and Dependability) and Telemetry/SLM (Silicon Lifecycle Management) architecture and methodology. With over 18 years of experience in the semiconductor industry, he has been involved in key phases of IP and SOC (System-on-Chip) development, including architecture, design, validation, and manufacturing testing. Dr. Su is also recognized as an accomplished researcher in emerging computing technology fields with publications, including a book, multiple book chapters, and over 60 papers in IEEE/ACM conferences and journals. He is the inventor of three granted patents, with three more pending. He has received awards such as the Best Paper Award at the IEEE International Conference on VLSI Design and the Outstanding Young Author Award from the IEEE Circuits and Systems Society. His research interests span architecture-level and circuit-level innovation, focusing on testability and dependability in various domains, including AI/ML hardware, cyber-physical systems and biochips, datacenter/high-performance computing, and autonomous systems.

Dr. Su actively contributes to cross-industry standardization efforts and plays a pivotal role in the technical ecosystem/community building, including development of the new IEEE workshops in the emerging fields. Dr. Su serves as an editorial board member for IEEE Design & Test (D&T) and has participated in organizing and technical program committees for several IEEE/ACM conferences. He has established strong research collaborations with top-tier universities and has been recognized with the SRC (Semiconductor Research Corporation) Outstanding Liaison Award in 2021 for his contributions.

Dr. Su received his B.S. and M.S. degrees in Automation from Tsinghua University in 1999 and 2001, respectively. He obtained his Ph.D. in Electrical and Computer Engineering from Duke University in 2006, where he received the Outstanding Dissertation Award from the European Design Automation Association (EDAA). He is a senior member of IEEE.

Biography (Yervant Zorian):

Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.

Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.

Biography (Jyotika Athavale):

Jyotika Athavale is a Director, Engineering Architecture at Synopsys, leading quality, reliability and safety research, pathfinding and architectures for data centers and automotive applications. She also serves as the 2024 President of the IEEE Computer Society, overseeing overall IEEE-CS programs, operations and service to the global computing community.

Jyotika leads and influences several international standardization initiatives in the area of RAS/safety in IEEE, ISO, SAE, JEDEC and OCP. She led the development of the IEEE 2851-2023 standard on Functional Safety Data Format for Interoperability, and now chairs the IEEE P2851.1 standardization initiative on Functional Safety interoperability with reliability. For her leadership in international safety standardization, Jyotika was awarded the 2023 IEEE SA Standards Medallion. And for her leadership in service, she was awarded the IEEE Computer Society Golden Core Award in 2022.

Jyotika has authored patents and many technical publications in various international conferences and journals. She has also pioneered & chaired international workshops and conferences in the field of dependable technologies.

 Tutorial 2 (14:30-17:00, August 18)

 Title: Scan-based DfT: Mitigating Vulnerabilities and Building Security Primitives

Speakers: Aijiao Cui (Harbin Institute of Technology (Shenzhen)), Gang Qu (Univ. of Maryland)

                          Aijiao Cui                                                          Gang Qu

Abstract:

Scan chain is one of the most powerful and popular design for test (DfT) technologies as it provides test engineers the unrestrictive access to the internal states of the core under test. This same convenience has also made scan chain an exploitable side channel for attackers to steal the cipher key of cryptographic core or combinational logic designed for obfuscation. In this tutorial, we will first present the preliminaries of scan-based DfT technology. Then we will illustrate the vulnerabilities against scan side-channel attacks and SAT attacks and review the existing countermeasures on how to design secure scan-based DfT to resist these attacks. Next, we will discuss how to utilize scan-based DfT as a security primitive to provide solutions for several hardware security problems including: hardware intellectual property protection, physical unclonable function and device authentication.

This tutorial targets two groups of audience: (1) graduate students interested in IC testing (in particular scan chain) and security, (2) researchers and engineers from industry and academic working on IC testing and hardware security. No prior knowledge on scan-based DfT or security is required to attend this tutorial. The audience is expected to learn the foundations and state-of-the-arts in secure scan design.

Biography (Aijiao Cui):

Aijiao Cui received the B.Eng. and M. Eng. degrees in electronics from Beijing Normal University, Beijing, China, in 2000 and 2003, respectively, and the Ph.D. degree in electrical and electronic engineering from Nanyang Technological University, Singapore, in 2009. From July 2003 to December 2004, she was a Lecturer with Beijing Jiaotong University, Beijing. She was a Research Fellow with Peking University Shenzhen SoC Laboratory, Shenzhen, from 2009 to 2010 prior to joining the School of Integrated Circuits of Harbin Institute of Technology (Shenzhen) in 2010, where she is currently a Professor. Her current research interests include hardware security and trusted IC design.

Biography (Gang Qu):

Gang Qu received the Ph.D. degree in computer science from the University of California, Los Angeles. He is currently a Professor with the Department of Electrical and Computer Engineering and the Institute for Systems Research, University of Maryland at College Park, where he leads the Maryland Embedded Systems and Hardware Security (MeshSec) Lab and the Wireless Sensors Laboratory. His primary research interests are in the area of embedded systems and VLSI CAD with a focus on low power system design and hardware related security and trust. Dr. Qu is a major contributor to the establishment of hardware security community. He has published more than 300 papers and delivered more than 150 keynotes, invited talks, and tutorials, most of them are on hardware security. He is a co-founder of the Asian Hardware-Oriented Security and Trust (AsianHOST) symposium in 2016, the Top Picks in Hardware and Embedded Security Workshop (Top Picks) in 2018, and the IEEE CEDA Hardware Security and Trust Technical Committee (HSTTC) in 2020. He has introduced hardware security track and served as track chair for many conferences, including DAC, ICCAD, ASPDAC, HOST, GLSVLSI (founding chair), SOCC (founding chair), and ISQED. He is an enthusiastic teacher, and has taught and co-taught various security courses. He is a fellow of IEEE.