2024 TCAD

pNeurFill: Enhanced Neural Network Model-Based Dummy Filling Synthesis With Perimeter Adjustment

Author: Zhaoting Chen, Junzhe Cai, Changhao Yan, Zhaori Bi, Yuzhe Ma, Bei Yu, Wenchuang Walter Hu, Dian Zhou, Xuan Zeng

Affiliation: Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong; Morefun Studios, Tencent Inc., Shanghai, China; Microelectronics Thrust, The Hong Kong University of Science and Technology (Guangzhou), Guangzhou, China; Precision Medicine Center, West China Hospital, Sichuan University, Chengdu, China; School of Microelectronics, State Key Laboratory of Integrated Chips and System, Fudan University, Shanghai, China; Department of Electrical Engineering, The University of Texas at Dallas, Richardson, TX, USA

Abstract:

Dummy filling is widely applied to significantly improve the planarity of topographic patterns for the chemical mechanical polishing (CMP) process in VLSI manufacturing. In the dummy filling flow, dummy synthesis works as the key step to adjust the post- CMP profile height. However, existing dummy synthesis optimization approaches usually fail to balance the filling quality and efficiency. This article proposes a novel model-based dummy filling synthesis framework NeurFill, integrated with multiple starting points-sequential quadratic programming (MSP-SQP) optimization solver. Inside this framework, a full-chip CMP simulator is first migrated to the neural network, achieving8134×speedup on gradient calculation by backward propagation. Entrenched in the CMP neural network models, we further implement an improved version of NeurFill (pNeurFill) to alleviate the post- CMP height variation caused by dummy perimeter. After each iteration of dummy density optimization, an additional perimeter adjustment based on a given candidate dummy pattern set is applied to search for the optimal perimeter fill amount. The experimental results show that the proposed NeurFill outperforms existing rule- and model-based methods. The extra perimeter adjustment strategy in pNeurFill can achieve an average 66.97Å decreasing in height variation and 8.92% quality improvement compared to NeurFill. This will provide guidance for DFM so as to increase IC chip yield.

 

 

 

 

2024 DAC

Minimizing Labeling, Maximizing Performance: A Novel Approach to Nanoscale Scanning Electron Microscope (SEM) Defect Segmentation

Author: Yibo Qiao, Weiping Xie, Shunyuan Lou, Qian Jin, Lichao Zeng, yining chen, QI SUN, Cheng Zhuo

Affiliation: Zhejiang University, University of Science and Technology of China

Abstract:

In semiconductor manufacturing, pinpointing nanoscale wafer defects is crucial for yield and reliability. Deep learning methods for defect segmentation rely heavily on large, labor-intensive datasets and focus mainly on macroscopic wafer defects, not nanoscale morphology. Our research introduces a hybrid weakly supervised scanning electron microscope (SEM) defect segmentation system with two sub-networks: one for accurate defect localization and image cropping, another for detailed segmentation. Validated on 1,328 SEM image defects from a real facility, our model surpasses existing weakly supervised methods and equals fully supervised models in accuracy, with 10% labeling effort, providing a novel approach for high precision defect segmentation.

 

 

 

 

2024 DAC

BNN-YEO: an Efficient Bayesian Neural Network for Yield Estimation and Optimization

Author: Zhenxing Dou, Ming Cheng, Ming Jia, Peng Wang

Affiliation: Beihang University, University of Bologna, XC Micro Technologies

Abstract:

Yield estimation and optimization is ubiquitous in modern circuit design but remains elusive for large-scale chips. This is largely due to the mounting cost of transistor-level simulation and one's often limited resources. In this study, we propose a novel framework to estimate and optimize yield using Bayesian Neural Network (BNN-YEO). By coupling machine learning method with Bayesian network, our approach can effectively integrate prior knowledge and is unaffected by the overfitting problem prevalent in most surrogate models. With the introduction of a smooth approximation of the indicator function, it incorporates gradient information to facilitate global yield optimization. We examine its effectiveness via numerical experiments on 6T SRAM and found that BNN-YEO provides 100x speedup (in terms of SPICE simulations) over standard Monte Carlo in yield estimation, and 20x faster than the state-of-the-art method for total yield estimation and optimization with improved accuracy.

 

 

 

 

2023 DATE

Robust Resistive Open Defect Identification Using Machine Learning with Efficient Feature Selection

Author: Zahra Paria Najafi-Haghi, Florian Klemme, Hanieh Jafarzadeh, Hussam Amrouch, Hans-Joachim Wunderlich

Affiliation: Institute of Computer Architecture and Computer Engineering, University of Stuttgart, Germany

Abstract:

Resistive open defects in FinFET circuits are reliability threats and should be ruled out before deployment. The performance variations due to these defects are similar to the effect of process variations which are mostly benign. In order not to sacrifice yield for reliability the effect of defects should be distinguished from process variations. It has been shown that machine learning (ML) schemes are able to classify defective circuits with high accuracy based on the maximum frequencies Fmax obtained under multiple supply voltages Vdd∈Vop. The paper at hand presents a method to minimize the number of required measurements. Each supply voltage Vdd defines a feature Fmax (Vdd). A feature selection technique is presented, which uses also the already available Fmax measurements. It is shown that ML-based techniques can work efficiently and accurately with this reduced number of Fmax (Vdd) measurements.

 

 

 

 

2022 TCAD

A Unified Framework for Layout Pattern Analysis With Deep Causal Estimation

Authors: Ran Chen; Shoubo Hu; Zhitang Chen; Shengyu Zhu; Bei Yu; Pengyun Li; Cheng Chen; Yu Huang

Affiliation: The Chinese University of Hong Kong, HiSilicon Technologies Co., Ltd., China

Abstract:

The decrease of feature size and the growing complexity of the fabrication process lead to more failures in manufacturing semiconductor devices. Therefore, identifying the root cause layout patterns of failures becomes increasingly crucial for yield improvement. In this article, a novel layout-aware diagnosis-based layout pattern analysis framework is proposed to identify the root cause efficiently. At the first stage of the framework, an encoder network trained using contrastive learning is used to extract representations of layout snippets that are invariant to trivial transformations, including shift, rotation, and mirroring, which are then clustered to form layout patterns. At the second stage, we model the causal relationship between any potential root cause layout patterns and the systematic defects by a structural causal model, which is then used to estimate the average causal effect (ACE) of candidate layout patterns on the systematic defect to identify the true root cause. Experimental results on real industrial cases demonstrate that our framework outperforms a commercial tool with higher accuracies and around ×8.4 speedup on average.

 

 

 

 

2022 ICCAD

WaferHSL: Wafer Failure Pattern Classification with Efficient Human-Like Staged Learning

Author: Qijing Wang, Martin D. F. Wong

Affiliation: CSE Department, CUHK

Abstract:

As the demand for semiconductor products increases and the integrated circuits (IC) processes become more and more complex, wafer failure pattern classification is gaining more attention from manufacturers and researchers to improve yield. To further cope with the real-world scenario that there are only very limited labeled data and without any unlabeled data in the early manufacturing stage of new products, this work proposes an efficient human-like staged learning framework for wafer failure pattern classification namedWaferHSL. Inspired by human's knowledge acquisition process, a mutually reinforcing task fusion scheme is designed for guiding the deep learning mode to simultaneously establish the knowledge of spatial relationships, geometry properties and semantics. Furthermore, a progressive stage controller is deployed to partition and control the learning process, so as to enable humanlike progressive advancement in the mode. Experimental results show that with only 10% labeled samples and no unlabeled samples, WaferHSL can achieve better results than previous SOTA methods trained with 60% labeled samples and a large number of unlabeled samples, while the improvement is even more significant when using the same size of labeled training set.

 

 

 

 

2021 ITC

Adaptive NN-based Root Cause Analysis in Volume Diagnosis for Yield Improvement

Authors: Xin Huang; Min Qin; Ruosheng Xu; Cheng Chen; Shangling Jui; Zhihao Ding; Pengyun Li; Yu Huang

Affiliation: HiSilicon Technologies Co., Ltd., China

Abstract:

Root Cause Analysis (RCA) is a critical technology for yield improvement in integrated circuit manufacture. Traditional RCA prefers unsupervised algorithms such as Expectation Maximization based on Bayesian models. However, these methods are severely limited by the weak predictive capability of statistical models and can’t effectively transfer the yield learning experience from old designs and processes to the new ones. Motivated by recent advancements of deep learning, in this paper we propose a Neural-Network-based adaptive framework for RCA in yield improvement. The proposed framework consists of an inference module and a self-adaptive module. The former receives volume diagnosis reports and predicts the root cause distributions. The latter is able to adapt the inference module to new designs and processes based on a few of targeted samples without any manual adjustment. Experimental results show that a relatively large improvement on accuracy is achieved by the proposed framework on simulated diagnosis data. Furthermore, the transferring capability of the self-adaptive module is also validated by the results.

 

 

 

 

2021 MDTS

A Machine Learning-based Approach for Failure Prediction at Cell Level based on Wafer Acceptance Test Parameters

Authors: Xiang Chen; Yi Zhao; Hongliang Lü; Xiaoqiang Shao; Cheng Chen; Yu Huang

Affiliation: HiSilicon Technologies Co., Ltd., China

Abstract:

Wafer Acceptance Test (WAT) or commonly known as Process Control Monitoring (PCM) includes numerous testing items that have many important applications, such as yield improvement and production cost control. The prediction of wafer yield based on WAT parameters has been successfully employed to reduce production costs spent on the circuit probing process. However, the relationship between WAT and subsequent diagnosis reports has not been sufficiently explored yet. This paper proposes a learning-based framework for failure prediction at cell level from WAT data, including various techniques for feature selection and handling imbalanced classes. Based on the selected parameters, machine learning models are employed to predict the failure of a given cell. The potential of the proposed methodology is evaluated over a set of industrial data. Experimental results demonstrate that our methodology can provide accurate test predictions (0.95+ accuracy, F1-score, and Area Under the Receiver Operating Characteristic curve (AUCROC)).

 

 

 

 

2021 ASP-DAC

Bayesian Inference on Introduced General Region: An Efficient Parametric Yield Estimation Method for Integrated Circuits

Author: Zhengqi Gao, Zihao Chen, Jun Tao, Yangfeng Su, Dian Zhou, Xuan Zeng

Affiliation: School of Microelectronics, Fudan University, University of Texas at Dallas

Abstract:

In this paper, we propose an efficient parametric yield estimation method based on Bayesian Inference. By observing that nowadays analog and mixed-signal circuit is designed via a multi-stage flow, and that the circuit performance correlation of early stage and late stage is naturally symmetrical, we introduce a general region to capture the common features of the early and late stage. Meanwhile, two private regions are also incorporated to represent the unique features of these two stages respectively. Afterwards, we introduce classifiers one for each region to explicitly encode the correlation information. Next, we set up a graphical model, and consequently adopt Bayesian Inference to calculate the model parameters. Finally, based on the obtained optimal model parameters, we can accurately and efficiently estimate the parametric yield with a simple sampling method. Our numerical experiments demonstrate that compared to the state-of-the-art algorithms, our proposed method can better estimate the yield while significantly reducing the number of circuit simulations.

 

 

 

 

2020 DAC

Wafer Map Defect Patterns Classification using Deep Selective Learning

Author: Mohamed Baker Alawieh, Duane Boning, and David Z Pan.

Affiliation: ECE Department, University of Texas at Austin, Austin, TX, USA

Abstract:

With the continuous drive toward integrated circuits scaling, efficient yield analysis is becoming more crucial yet more challenging. In this paper, we propose a novel methodology for wafer map defect pattern classification using deep selective learning. Our proposed approach features an integrated reject option where the mode chooses to abstain from predicting a class label when misclassification risk is high. Thus, providing a trade-off between prediction coverage and misclassification risk. This selective learning scheme allows for new defect class detection, concept shift detection, and resource allocation. Besides, and to address the class imbalance problem in the wafer map classification, we propose a data augmentation framework built around a convolutional auto-encoder mode for synthetic sample generation. The efficacy of our proposed approach is demonstrated on the WM-811k industrial dataset where it achieves 94% accuracy under full coverage and 99% with selective learning while successfully detecting new defect types.

 

 

 

 

2019 ITC

Improving Test Chip Design Efficiency via Machine Learning

Author: Zeye Liu, Qicheng Huang, Chenlei Fang, and R. D. (Shawn) Blanton.

Affiliation: Department of Electrical and Computer Engineering, Advanced Chip Testing Laboratory, Carnegie Mellon University

Abstract:

Competitive position in the semiconductor field depends on yield which is becoming more challenging to achieve high levels due to the increasing complexity associated with the design and fabrication of leading-edge integrated circuits (ICs). Consequently, test chips, especially full-flow logic test chips, are increasingly employed to investigate the complex interaction between layout features and the process before and during product ramp. However, designing a high quality full-flow logic test chip can be time-consuming due to the huge design space. This work describes a design methodology that deploys a random forest classification technique to predict synthesis outcomes for test chip design exploration. Experiments on creating five full-flow logic test chips, which mimic five different designs, demonstrate the efficacy of the proposed methodology. To be specific, those design experiments demonstrate that the machine learning aided flow speeds up design by 11× with negligible performance degradation.

 

 

 

 

AI+EDA

Yield learning