1 Background and Objectives
Given the substantial threats posed by quantum computing to conventional cryptographic systems (e.g., RSA, ECC), the U.S. National Institute of Standards and Technology (NIST) has formalized its Post-Quantum Cryptography (PQC) standards. This compe- tition challenges participating teams to design high-throughput, low-latency, and power- efficient hardware acceleration Intellectual Properties (IPs) targeting Field-Programmable Gate Array (FPGA) platforms. The focus lies on two core algorithms standardized by NIST:
1) ML-KEM (formerly Kyber): Key Encapsulation Mechanism (KEM)
2) ML-DSA (formerly Dilithium): Digital Signature Scheme (DSS)
2 Key Schedule
• Registration Period: Open Now – March 15, 2026
• Preliminary Round Submission Deadline: April 26, 2026 (Submission of sim- ulation proposals and preliminary technical • reports required)
• Final Round Submission Deadline: May 24, 2026 (Submission of final project deliverables, comprehensive technical reports, and academic papers required)
• Winner Announcement Date: May 29, 2026
3 Registration and Hardware Platform Specifications
• Eligible Participants: University students (undergraduate, master’s, and doctoral levels) and enterprise engineers worldwide
• Team Composition Requirements: 1–3 team members per group, with 1–2 optional academic or industrial advisors
• Designated Hardware Platform: AMD Xilinx Kria K26 System-on-Module (SOM) (All core designs shall be implemented on the Programmable Logic)
• Registration Portal: Google Form Registration
4 Scoring Criteria (Total 100 Points)
Scoring Principle: On-board measured execution speed shall be the primary evaluation metric, supplemented by tool-estimated power consumption.
4.1 Constraints and Compliance (Prerequisite for Valid Submission)
• Resource Utilization: All resource consumption metrics must strictly adhere to the hardware constraints of the K26 SOM chip
• Timing Closure: The design must successfully pass implementation with zero timing violations (i.e., Worst Negative Slack, WNS ≥ 0)
• Functional Correctness: The design must pass full verification against the official Known Answer Tests (KAT) vectors
• Minimum Speed Threshold: The measured latency for a single operation (Tuser) must satisfy Tuser ≤ 3×Tavg , where Tavg denotes the average latency across all valid submissions. Non-compliant designs will be deemed invalid.
4.2 Efficiency Score (80 Points)
The Energy-Delay Product (EDP) model is adopted as the core metric for efficiency scoring, calculated using the following formula:
where the cost function Cost is defined as:
• Powerdynamic: PL dynamic power consumption derived from Vivado Report Power (measured at 25C with default switching activity settings)
• Ttotal: Total latency measured on hardware for 100 consecutive algorithm operations
4.3 Technical Report Score (20 Points)
• Architecture Design (10 pts): Rationality and innovativeness of pipeline opti- mization, parallelism deployment, and datapath architecture design
• Optimization Strategy (5 pts): Effectiveness of low-power design methodologies and specificity of timing optimization techniques
• Documentation Quality (5 pts): Logical coherence of technical exposition and completeness of reproducibility procedures
5 Deliverables Specifications
This competition mandates a three-track submission framework of ”Project Source Code + Technical Report + Academic Paper”. All award-winning submissions will be required to be open-sourced for academic and industrial advancement.
5.1 Complete Project Source Code Package
The package shall include PL-side RTL/HLS source code, PS-side host control code, hard- ware constraint files, and end-to-end build scripts (Tcl/Makefile). The root directory must contain a ‘README.md’ file specifying the software/hardware environment versions and step-by-step reproducibility guidelines, covering the entire workflow from logic synthesis to on-board validation.
5.2 Technical Report (PDF Format)
The report shall provide a detailed elaboration of the system architecture, operator reuse strategies, memory hierarchy optimization schemes, and comprehensive perfor- mance/power consumption analysis with experimental data.
5.3 Academic Paper (PDF Format)
The paper must strictly comply with the submission guidelines of IEEE ITC- Asia 2026, adopting the standard IEEE conference template with a maximum length of 6 pages. This paper serves as a critical reference for the Excellence Award evaluation and must explicitly elaborate on the technical novelty of the proposed design and conduct a thorough performance comparison with the State-of-the-Art (SOTA) works.
6 Awards & Recognition
• 1st Prize Winner: Cash Award of USD 1,450 or CNY 10,000
• 2nd Prize Winner: Cash Award of USD 1,150 or CNY 8,000
• 3rd Prize Winner: Cash Award of USD 850 or CNY 6,000
• Excellence Award: Honorary Recognition (awarded to 3 teams, no cash prize)
Special Recognition for All Winning Teams: The academic papers submitted by all prize-winning teams will be directly recommended for peer-reviewed acceptance at the associated publication venue.
Contact Email: c130044@163.com
Teams Communication Group: Click to Join
Reference Repository for Software Algorithms and Paper Templates: https://github.com/Itc-asia/PQC_FPGA.git
Official Competition Website: https://www.castest.com.cn/itcasia2026_competition
