Keynotes
01 Title: Lifetime Health for Multi-Die Systems in the Era of AI
Abstract:
As traditional semiconductor innovation moves beyond transistor scaling in monolithic chips, multi-die architectures based on wide range of chiplets are emerging as the foundation of next-generation intelligent systems. While these innovative solutions enable unprecedented levels of performance and scalability, they also introduce new challenges in test, quality, reliability, thermal and lifecycle management. This keynote explores the design methodologies, DFT strategies, and reliability frameworks required to ensure robust, high-quality chiplet and multi-die systems, highlighting the critical role of advanced self-test, repair and SLM technologies in enabling the future proliferation of such systems.
Bio:
Dr. Yervant Zorian is a Chief Architect and Fellow at Synopsys, as well as President of Synopsys Armenia. Formerly, he was Vice President and Chief Scientist of Virage Logic, Chief Technologist at LogicVision, and a Distinguished Member of Technical Staff AT&T Bell Laboratories. He is currently the President of IEEE Test Technology Technical Council (TTTC), the founder and chair of the IEEE 1500 Standardization Working Group, the Editor-in-Chief Emeritus of the IEEE Design and Test of Computers and an Adjunct Professor at University of British Columbia. He served on the Board of Governors of Computer Society and CEDA, was the Vice President of IEEE Computer Society, and the General Chair of the 50th Design Automation Conference (DAC) and several other symposia and workshops.
Dr. Zorian holds 35 US patents, has authored four books, published over 350 refereed papers and received numerous best paper awards. A Fellow of the IEEE since 1999, Dr. Zorian was the 2005 recipient of the prestigious Industrial Pioneer Award for his contribution to BIST, and the 2006 recipient of the IEEE Hans Karlsson Award for diplomacy. He received the IEEE Distinguished Services Award for leading the TTTC, the IEEE Meritorious Award for outstanding contributions to EDA, and in 2014, the Republic of Armenia's National Medal of Science. He received an MS degree in Computer Engineering from University of Southern California, a PhD in Electrical Engineering from McGill University, and an MBA from Wharton School of Business, University of Pennsylvania.
02 Title: The Coverage Illusion: Why Failures are Increasingly Evading Traditional Fault Models
Abstract:
The widespread use of abstract fault models for generating digital IC test stimuli reduces an otherwise intractable exponential input space to a manageable, finite fault list, typically evaluated in seconds of tester time. Down to approximately 32nm process nodes, this paradigm successfully delivered outgoing DPPM levels that met industrial requirements; stuck-at fault coverage above 99% and transition-delay coverage around 95% served as reliable proxies for true defect coverage. Over the past two decades, however—and especially in recent sub-10nm processes—the correlation between these abstract fault models and actual manufacturing defects has weakened considerably, as defects now increasingly encompass device parameter shifts and random process variations. Consequently, even when scan tests achieve their fault-model coverage goals, unacceptable rates of test escapes are being observed in the field, including notable incidents of silent data corruption in hyperscale datacenters. This presentation will explain the underlying limitations that cause real failures to slip past popular fault models and discuss recent research efforts aimed at closing these critical test gaps.
Bio:
Adit D. Singh received the B.Tech. from IIT Kanpur (1976), and the M.S. and Ph.D. (1982) from Virginia Tech, all in Electrical Engineering. He currently holds the Godbold Endowed Chair in Electrical and Computer Engineering at Auburn University; earlier, from 2002 to 2020, he was James B. Davis Professor. He has also served on the faculty at the University of Massachusetts in Amherst, and Virginia Tech in Blacksburg, and has held formal appointments during sabbaticals as visiting/guest professor at the University of Stuttgart, Germany (2025), the University of Tokyo, Japan (2018), and the University of Freiburg, Germany (2012). He was a Fulbright Awardee at the University Polytechnic of Catalonia in Barcelona, Spain (1999-2000), and a Max-Planck Researcher at the University of Potsdam, Germany (1997-98). He also regularly lectures away from campus, having taught well over 100 invited tutorials and short courses at conferences, universities and in-house at companies. His academic interests span all aspects of VLSI technology, with particular emphasis on integrated circuit (IC) test and reliability. He is especially recognized for pioneering contributions to statistical methods in test and adaptive testing. He has authored over 300 research papers and holds international patents that have been licensed to industry. He has also served as a consultant to major semiconductor technology companies, including as an expert witness for high-profile patent litigation cases. He was elected Fellow of IEEE in 2002 "for contributions to defect-based testing and test optimization in VLSI circuits".
Professor Singh has held leadership roles as General Chair/Co-Chair/Program Chair for dozens of international VLSI design and test conferences. He has held many volunteer leadership roles in the world’s largest technical professional society, IEEE, including two elected terms as Chair of the IEEE Test Technology Technical Council (2007-11), and on the Board of Governors of the IEEE Council on Design Automation (2011-2015). He is a Life Fellow of IEEE and Golden Core member of the IEEE Computer Society.
Adit D. Singh, Auburn University
Gang Qu, University of Maryland at College Park
Yu Huang, HiSilicon
Yervant Zorian, President of Synopsys Armenia
04 Title: AI for DFT & Yield Learning
03
Bio:
Gang Qu received the Ph.D. degree in computer science from the University of California, Los Angeles. He is currently a Professor with the Department of Electrical and Computer Engineering and the Institute for Systems Research, University of Maryland at College Park, where he leads the Maryland Embedded Systems and Hardware Security (MeshSec) Lab and the Wireless Sensors Laboratory. His primary research interests are in the area of embedded systems and VLSI CAD with a focus on low power system design and hardware related security and trust. Dr. Qu is a major contributor to the establishment of hardware security community. He has published more than 300 papers and delivered more than 150 keynotes, invited talks, and tutorials, most of them are on hardware security. He is a co-founder of the Asian Hardware-Oriented Security and Trust (AsianHOST) symposium in 2016, the Top Picks in Hardware and Embedded Security Workshop (Top Picks) in 2018, and the IEEE CEDA Hardware Security and Trust Technical Committee (HSTTC) in 2020. He has introduced hardware security track and served as track chair for many conferences, including DAC, ICCAD, ASPDAC, HOST, GLSVLSI (founding chair), SOCC (founding chair), and ISQED. He is an enthusiastic teacher, and has taught and co-taught various security courses. He is a fellow of IEEE.
Abstract:
This talk will present a comprehensive overview of how recent breakthroughs in artificial intelligence (AI) and machine learning (ML) are fundamentally transforming Design for Testability (DFT) and Yield Learning in advanced semiconductor manufacturing. The presentation synthesizes key published works from leading industry players and academic institutions, highlighting successful deployments of AI-driven methodologies in DFT, ATPG, DRC and data-driven root cause analysis. Special emphasis will be placed on how AI accelerates silicon feedback loops, enabling predictive yield modeling, early defect detection, and autonomous test flow optimization. Furthermore, the talk will examine emerging trends and future trajectories, including the integration of AI-native EDA workflows for IC testing. Attendees will gain actionable insights into deploying AI solutions in production test environments, addressing critical engineering challenges such as data governance, model generalization across process nodes, and hardware-aware acceleration, while exploring the roadmap toward fully intelligent, closed-loop semiconductor test ecosystems.
Bio:
Dr. Yu Huang is an EDA expert with over 25 years of experience, currently serving as the Chief Scientist for EDA at HiSilicon, and concurrently holding the positions of Semiconductor Domain Scientist at Huawei and Director of the HiSilicon Algorithm Committee. As an IEEE Senior Member, he possesses deep expertise in IC testing and the application of AI in EDA. Dr. Huang’s career has primarily focused on translating cutting-edge research into commercial EDA products. Between 2000 and 2020, he worked for Mentor Graphics / Siemens EDA for two decades, leading the R&D of multiple commercial EDA tools. After joining HiSilicon in 2020, he took full responsibility for the methodology, flow, architecture, and algorithm development of EDA tools. Highly regarded in both academia and industry, he holds more than 40 granted U.S. and Chinese patents and has over 50 pending patents. He has authored or co-authored more than 170 peer-reviewed publications. In the technical domain, Dr. Huang is a principal researcher and developer of large-scale commercial software, specializing in tool development involving millions of lines of C++ code. His core expertise includes DFT, ATPG, Test Compression, BIST, Diagnosis, and Yield Learning for ultra-large-scale SoCs. He has extensive hands-on experience in hardware diagnosis and silicon debug, having handled complex real-world cases at leading international semiconductor companies such as TSMC, Intel, AMD, and HiSilicon. In recent years, Dr. Huang has actively explored the application of machine learning and AI in EDA, excelling in optimizing DRC, Diagnosis, Yield Learning, and DFT planning using Bayesian inference, SVM, Deep Learning, and LLM technologies. He has unique advantages in DFT/ATPG for large AI chips. His research has gained international recognition; for instance, his work on the design of layout-friendly EDT decompressors received the Best Paper Award at IEEE VTS 2020. Beyond technical R&D, Dr. Huang is actively involved in international academic exchanges and organization. He is the founder of the International Symposium of EDA (ISEDA) and has served as Program Committee Chair or invited keynote speaker at major international conferences such as IEEE ITC, ETS, DAC, ATS, and NATW. He has also served as a guest or visiting professor at universities including Tsinghua University, Fudan University, and Xidian University, mentoring doctoral students and promoting industry-academia-research collaboration. His educational background includes a Ph.D. in Electrical and Computer Engineering from the University of Iowa, an M.Sc.in Semiconductor Devices and Physics, a B.Sc. in Electrical Engineering, and a second bachelor’s degree in International Business and Management from Nankai University, China.
