Tutorial 2 (14:00-17:00, August 19)
Title : The Evolution of DFT Techniques for AI Devices from Tiled based design, in-field Testing and Beyond
Speaker : Lee Harrison (Marketing Director, Tessent product division, Siemens EDA)
Lee Harrison
Abstract:
The expanding use and development of AI are driving the evolution of advanced AI hardware. This tutorial will cover the critical characteristics and architectures of popular AI hardware designs and how these can be leveraged from a design-for-test (DFT) perspective. The tutorial will also explore how DFT technologies are continuously evolving to meet these advanced requirements, including monitoring techniques that address new challenges related to reliability and resilience. Finally, we will present several case studies demonstrating how DFT is implemented in real-world AI chips.
Biography:
Lee Harrison is Director, Product Marketing, with Siemens Tessent Division. He has over 25 years of industry experience working with Siemens Tessent DFT products, with a focus on safety and security, Lee is working to ensure that current and future DFT requirements of Siemens’s Automotive and HPC customers are understood and met. Lee Received his BEng in MicroElectronic Engineering from Brunel University London in 1996. Lee presents regularly at industry conferences such as DAC, ITC, VTS, ETS, DATE etc.
Lee Harrison
TUTORIALS
Tutorial 1 (9:00-12:00, August 19)
Title: Secure Scan-based DfT
Speaker: Gang Qu (University of Maryland）
Gang Qu
Abstract:
Faults are inevitable in integrated circuit (IC) fabrication due to many factors such as manufacturing process variability. By adding testability features at design time, scan-based design makes test pattern generation, application and evaluation cost-effective to screen out defective ICs. It has become a common design structure for modern chips. However, the unrestrictive and ease of access to the internal states of the circuit under test makes scan chains an exploitable side channel for attacker to steal sensitive information such as cipher key of cryptographic core through in-field testing.
In this tutorial, after a brief introduction of scan-based DfT, we will focus on its security vulnerabilities, the attacks based on these vulnerabilities, and corresponding countermeasures. We will also discuss DfT-based solutions to some of the hardware security problems, including digital watermarking, fingerprinting, IC metering, physical unclonable function, and random number generation.
Biography:
Gang Qu received the Ph.D. degree in computer science from the University of California, Los Angeles. He is currently a Professor with the Department of Electrical and Computer Engineering and the Institute for Systems Research, University of Maryland at College Park, where he leads the Maryland Embedded Systems and Hardware Security (MeshSec) Lab and the Wireless Sensors Laboratory. His primary research interests are in the area of embedded systems and VLSI CAD with a focus on low power system design and hardware related security and trust. Dr. Qu is a major contributor to the establishment of hardware security community. He has published more than 300 papers and delivered more than 150 keynotes, invited talks, and tutorials, most of them are on hardware security. He is a co-founder of the Asian Hardware-Oriented Security and Trust (AsianHOST) symposium in 2016, the Top Picks in Hardware and Embedded Security Workshop (Top Picks) in 2018, and the IEEE CEDA Hardware Security and Trust Technical Committee (HSTTC) in 2020. He has introduced hardware security track and served as track chair for many conferences, including DAC, ICCAD, ASPDAC, HOST, GLSVLSI (founding chair), SOCC (founding chair), and ISQED. He is an enthusiastic teacher, and has taught and co-taught various security courses. He is a fellow of IEEE.
