2023 DAC

RL-CCD: Concurrent Clock and Data Optimization using Attention-Based Self-Supervised Reinforcement Learning

Author:Yi-Chen Lu, Wei-Ting Chan, Deyuan Guo, Sudipto Kundu, Vishal Khandelwal, Sung Kyu Lim

Affiliation:Synopsys Inc., Mountain View, CA; Synopsys Inc., Hillsboro, OR; School of ECE, Georgia Institute of Technology, Atlanta, GA

Abstract:

Concurrent Clock and Data (CCD) optimization is a well-adopted approach in modern commercial tools that resolves timing violations using a mixture of clock skewing and delay fixing strategies. However, existing CCD algorithms are flawed. Particularly, they fail to prioritize violating endpoints for different optimization strategies correctly, leading to flow-wise globally sub-optimal results. In this paper, we overcome this issue by presenting RL-CCD, a Reinforcement Learning (RL) agent that selects endpoints for useful skew prioritization using the proposed EP-GNN, an endpoint-oriented Graph Neural Network (GNN) mode, and a Transformer-based self-supervised attention mechanism. Experimental results on 19 industrial designs in 5 − 12nm technologies demonstrate that RL-CCD achieves up to 64% Total Negative Slack (TNS) reduction and 66.5% number of violating endpoints (NVE) improvement over the native implementation of a commercial tool.

2020 ISLPED

Pre-layout clock tree estimation and optimization using artificial neural network

Author:Sunwha Koh, Yonghwi Kwon, Youngsoo Shin

Affiliation:Korea Advanced Institute of Science and Technology;

Abstract:

Clock tree synthesis (CTS) takes place in a very late design stage, so most of the time, power consumption is analyzed while a circuit does not contain a clock tree. We build an artificial neural network (ANN) to estimate the number of clock buffers and apply to each clock gater as well as clock source in ideal clock network. Clock structure is then constructed using such estimated clock buffers. Experiments with a few test circuits demonstrate very high accuracy of this method, average clock power estimation error less than 5%. The proposed method also allows us to find the possible minimum number of clock buffers with optimized clock parameters (e.g. target skew, clock transition time). The possible minimum number of buffers can be found by binary search algorithm and on each step of the algorithm, trained ANN is used to find such clock parameters for the target number of buffers. Using proposed clock parameter optimization, we found that the number of buffers in clock network can be reduced by 31%, on average.

2019 ICCAD

GAN-CTS A Generative Adversarial Framework for Clock Tree Prediction and Optimization

Author:Yi-Chen Lu, Jeehyun Lee, Anthony Agnesina, Kambiz Samadi, Sung Kyu Lim

Affiliation:School of ECE, Georgia Institute of Technology, Atlanta, GA;Qualcomm Technologies, Inc., San Diego, CA

Abstract:

In this paper, we propose a complete framework named GAN-CTS which utilizes conditional generative adversarial network (GAN) and reinforcement learning to predict and optimize clock tree synthesis (CTS) outcomes. To precisely

characterize different netlists, we leverage transfer learning to extract design features directly from placement images. Based on the proposed framework, we further quantitatively interpret the importance of each CTS input parameter subject to various design objectives. Finally, to prove the generality of our

framework, we conduct experiments on the unseen netlists which are not utilized in the training process. Experimental results performed on industrial designs demonstrate that our framework (1) achieves an average prediction error of 3%, (2) improves the commercial tool’s auto-generated clock tree by 51.5% in clock

power, 18.5% in clock wirelength, 5.3% in the maximum skew, and (3) reaches an F1-score of 0.952 in the classification task of determining successful and failed CTS processes.

AI+EDA

Clock tree optimization