2023 ICCAD

Invited Paper: IEEE CEDA DATC Emerging Foundations in IC Physical Design and MLCAD Research

Author: Jinwook Jung, Andrew B. Kahng, Sayak Kundu, Zhiang Wang, Dooseok Yoon

Affiliation: UC San Diego, La Jolla, CA, USA; IBM T. J. Watson Research Center, NY, USA

Abstract:

Recent activities of the IEEE CEDA DATC strengthen the DATC Robust Design flow (RDF) and broadly support research on machine learning for CAD/EDA (MLCAD). The RDF-2023 version of the RDF adds standalone and integrated netlist partitioners, a detailed placement optimizer, dynamic power analysis, and enablement of new directions (design-technology co-optimization and 3D layout). Advancement of benchmarking practices and strong baselines has continued - e.g., the MacroPlacement effort introduced in RDF-2022 now has new benchmarks, integration of the AutoDMP macro placer, and baseline solutions generated by Simulated Annealing and human experts. Other DATC efforts have focused on proxies and other elements of MLCAD research enablement. These include real and synthetic benchmarks tailored for IR drop analysis, a calibration methodology for research PDKs, and artificial netlist generation for data augmentation and design space coverage of netlists used in mode training. We conclude with directions for future DATC efforts.

 

 

 

 

2023 ASP-DAC

Graph Neural Networks: A Powerful and Versatile Tool for Advancing Design, Reliability, and Security of ICs

Author: Lilas Alrahis, Johann Knechtel, Ozgur Sinanoglu

Affiliation: NewYork University Abu Dhabi Abu Dhabi, United Arab Emirates (UAE)

Abstract:

Graph neural networks (GNNs) have pushed the state-of-the-art (SOTA) for performance in learning and predicting on large-scale data present in social networks, biology, etc. Since integrated circuits (ICs) can naturally be represented as graphs, there has been a tremendous surge in employing GNNs for machine learning (ML)-based methods for various aspects of IC design. Given this trajectory, there is a timely need to review and discuss some powerful and versatile GNN approaches for advancing IC design. In this paper, we propose a generic pipeline for tailoring GNN modes toward solving challenging problems for IC design. We out-line promising options for each pipeline element, and we discuss selected and promising works, like leveraging GNNs to break SOTA logic obfuscation. Our comprehensive overview of GNNs frame-works covers (i) electronic design automation (EDA) and IC design in general, (ii) design of reliable ICs, and (iii) design as well as analysis of secure ICs. We provide our overview and related resources also in the GNN4IC hub at https://github.com/DfX-NYUAD/GNN4IC. Finally, we discuss interesting open problems for future research.

 

 

 

 

2023 Science China Information Sciences

Chip design with machine learning: a survey from algorithm perspective

Author: Wenkai He, Xiaqing Li, Xinkai Song, Yifan Hao, Rui Zhang, Zidong Du & Yunji Chen

Affiliation: State Key Lab of Processor, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

Abstract:

Chip design with machine learning (ML) has been widely explored to achieve better designs, lower runtime costs, and no human-in-the-loop process. However, with tons of work, there is a lack of clear links between the ML algorithms and the target problems, causing a huge gap in understanding the potential and possibility of ML in future chip design. This paper comprehensively surveys existing studies in chip design with ML from an algorithm perspective. To achieve this goal, we first propose a novel and systematical taxonomy that divides target problems in chip design into three categories. Then, to solve the target problems with ML algorithms, we formulate the three categories as three ML problems correspondingly. Based on the taxonomy, we conduct a comprehensive survey in terms of target problems based on different ML algorithms. Finally, we conclude three key challenges for existing studies and highlight several insights for the future development of chip design with machine learning. By constructing a clear link between chip design problems and ML solutions, we hope the survey can shed light on the road to chip design intelligence from previous chip design automation.

 

 

 

 

2023 Bulletin of Chinese Academy of Sciences

From chip design to chip learning

Author: Yunji CHEN, Zidong DU, Qi GUO, Wei LI, Yijun TAN

Affiliation: State Key Lab of Processor, Institute of Computing Technology, Chinese Academy of Sciences, Beijing, 100190, China

Abstract:

Chip is the foundation of the modern information society. As the world is entering a new era of human-cyber-physical ternary computing, with diverse intelligent applications over trillions of devices, chip with specialized architecture will be heavily demanded in both numbers and types. However, chip design is very costly, which usually requires a long design cycle, complicated process, and high professional developers. Hence, there is a large gap between the need of tremendous chips and the high cost of chip design in the new era. This study proposes Chip Learning, a learning-based method to perform the entire chip design, including logic design, circuit design, and physical design. As an alternate to chip design, Chip Learning aims to remove the barrier of professional knowledge and experiences for effective chip design with a no-human-in-the-loop process in a short time.

 

 

 

 

2022 ICCAD

Why are Graph Neural Networks Effective for EDA Problems?: (Invited Paper)

Author: Haoxing Ren, Siddhartha Nath, Yanqing Zhang, Hao Chen, Mingjie Liu

Affiliation: NVIDIA Corporation, University of Texas at Austin

Abstract:

In this paper, we discuss the source of effectiveness of Graph Neural Networks (GNNs) in EDA, particularly in the VLSI design automation domain. We argue that the effectiveness comes from the fact that GNNs implicitly embed the prior knowledge and inductive biases associated with given VLSI tasks, which is one of the three approaches to make a learning algorithm physics-informed. These inductive biases are different to those common used in GNNs designed for other structured data, such as social networks and citation networks. We will illustrate this principle with several recent GNN examples in the VLSI domain, including predictive tasks such as switching activity prediction, timing prediction, parasitics prediction, layout symmetry prediction, as well as optimization tasks such as gate sizing and macro and cell transistor placement. We will also discuss the challenges of applications of GNN and the opportunity of applying self-supervised learning techniques with GNN for VLSI optimization.

 

 

 

 

2022 ASP-DAC

Reinforcement Learning for Electronic Design Automation: Case Studies and Perspectives: (Invited Paper)

Author: Ahmet Faruk Budak, Zixuan Jiang, Keren Zhu, Azalia Mirhoseini, Anna Goldie, David Z. Pan

Affiliation: The University of Texas at Austin

Abstract:

Abstract:Reinforcement learning (RL) algorithms have recently seen rapid advancement and adoption in the field of electronic design automation (EDA) in both academia and industry. In this paper, we first give an overview of RL and its applications in EDA. In particular, we discuss three case studies: chip macro placement, analog transistor sizing, and logic synthesis. In collaboration with Google Brain, we develop a hybrid RL and analytical mixed -size placer and achieve better results with less training time on public and proprietary benchmarks. Working with Intel, we develop an RL-inspired optimizer for analog circuit sizing, combining the strengths of deep neural networks and reinforcement learning to achieve state-of-the-art black-box optimization results. We also apply RL to the popular logic synthesis framework ABC and obtain promising results. Through these case studies, we discuss the advantages, disadvantages, opportunities, and challenges of RL in EDA.

 

 

 

 

2022 ARXIV

Towards Machine Learning for Placement and Routing in Chip Design: a Methodological Overview

Authors: Junchi Yan, Xianglong Lyu, Ruoyu Cheng, Yibo Lin

Affiliation: Department of CSE, and MoE Key Lab of Artificial Intelligence, Shanghai Jiao Tong University; Department of EECS, Peking University

Abstract:

Placement and routing are two indispensable and challenging (NP-hard) tasks in modern chip design flows. Compared with traditional solvers using heuristics or expert-well-designed algorithms, machine learning has shown promising prospects by its data-driven nature, which can be of less reliance on knowledge and priors, and potentially more scalable by its advanced computational paradigms (e.g. deep networks with GPU acceleration). This survey starts with the introduction of basics of placement and routing, with a brief description on classic learning-free solvers. Then we present detailed review on recent advance in machine learning for placement and routing. Finally we discuss the challenges and opportunities for future research.

 

 

 

 

2021 ICCAD

METRICS2.1 and flow Tuning in the IEEE CEDA Robust Design flow and OpenROAD ICCAD Special Session Paper

Author: Jinwook Jung, Andrew B. Kahng, Seungwon Kim, Ravi Varadarajan

Affiliation: IBM T. J. Watson Research Center, Yorktown Heights, NY, USA; UC San Diego, La Jolla, CA, USA

Abstract:

Abstract:In today's RTL-to-GDS flow domain, there is a lack of standards for reporting of design and tool metrics. Moreover, each tool or engine has its own set of parameters that can change outcomes and trade off PPA and other metrics. Thus, the study and optimization of impacts of parameter settings across the entire RTL- to-GDS tool chain has been largely ad hoc. In this paper, we first describe METRICS2.1, a proposed standard for RTL-to-GDS design tool and flow metrics. We then describe how data collected using a METRICS2.1 realization can be analyzed to give insight into flow tuning and fields of use for PPA optimization. Last, we discuss hyperparameter autotuning in the RTL-to-GDS flow. We present AutoTuner, which uses derivative-free optimization to handle challenges of non-differentiability and many local minima. An open repository based on METRICS2.1 has been established for sharing of reproducible, standardized metrics data, along with example implemented applications, to support academic and industrial research on machine learning for tool/flow tuning

 

 

 

 

2021 ICCAD

Optimizing VLSI Implementation with Reinforcement Learning - ICCAD Special Session Paper

Author: Haoxing Ren, Saad Godil, Brucek Khailany, Robert Kirby, Haiguang Liao, Siddhartha Nath, Jonathan Raiman, Rajarshi Roy

Affiliation: NVIDIA Corporation; Carnegie Mellon University

Abstract:

Reinforcement learning (RL) has gained attention recently as an optimization algorithm for chip design. This method treats many chip design problems as Markov decision problems (MDPs), where design optimization objectives are converted into rewards given by the environment and design variables are converted into actions provided to the environment. Some recent examples include applications of RL to macro placement and standard cell layout routing. We believe RL can be applied to nearly all aspects of VLSI implementation flows, since many VLSI implementation problems are often NP-complete and state-of-art algorithms cannot be guaranteed to be optimal. With enough training data, it is possible to achieve better results with RL. In this paper we review recent advances in applying RL to VLSI implementation problems such as cell layout, synthesis, placement, routing and parameter tuning. We discuss the challenges of applying RL to VLSI implementation flows and propose future research directions for overcoming these challenges.

 

 

 

 

TODAES 2021

Machine Learning for Electronic Design Automation: A Survey

Authors: Guyue Huang, Jingbo Hu, Yifan He, Jialong Liu, Mingyuan Ma, Zhaoyang Shen, Juejian Wu, Yuanfan Xu, Hengrui Zhang, Kai Zhong, Xuefei Ning, Yuzhe Ma, Haoyu Yang, Bei Yu, Huazhong Yang, and Yu Wang

Affiliation: Tsinghua University, China, Chinese University of Hong Kong, Hong Kong SAR

Abstract:

With the down-scaling of CMOS technology, the design complexity of very large-scale integrated is increasing. Although the application of machine learning (ML) techniques in electronic design automation (EDA) can trace its history back to the 1990s, the recent breakthrough of ML and the increasing complexity of EDA tasks have aroused more interest in incorporating ML to solve EDA tasks. In this article, we present a comprehensive review of existing ML for EDA studies, organized following the EDA hierarchy.

 

 

 

 

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